FPGA Glitch Power Analysis and Reduction

Fig. 4.Experimental flow.V. EXPERIMENTAL STUDYWe perform our glitch reduction algorithm on 20 MCNCbenchmark circuits. The experimental methodology was chosento include commercial CAD tools wherever possible,to evaluate the efficacy of the algorithm on real-world FP-GAs. The flow is shown in Figure 4. We perform a fullcompilation using Quartus II 10.1 (synthesis, placement androuting) targeting the Altera Stratix III 65nm FPGA family [1].This is followed by a timing simulation using ModelSimSE 6.3e. For each circuit, 5000 random input vectors areapplied. We use a set of custom scripts to transform thesimulation netlist generated by Quartus into BLIF format,which can then be read into ABC, where the glitch reductionis performed. Combinational equivalence checking (commandcec in ABC [13]) is used after the glitch reduction step toensure that the functionality of the circuit remains the same.The output from ABC is used to modify the configurationbits in the simulation netlist, thus ensuring that the placementand routing remain identical. Three passes of the optimizationloop are performed. Experiments show that very few changes,if any, are made after this point. The power measurements areperformed using Quartus PowerPlay.A. ResultsThe leftmost bars in Figure 5(a) (vs. baseline) represent thepercentage reduction in total core dynamic power after performingthe glitch reduction algorithm. The average reductionis 4.0%, with a peak of 12.5%. Figure 5(b) shows the correspondingreduction in glitch power. The average reduction is13.7%, with a peak of 84.0%. Naturally, the amount of powerreduction possible is based on the amount of glitching presentand the number of don’t-cares available. While the overallaverage power reductions are relatively modest, we believethey will interest FPGA vendors and power-sensitive FPGAcustomers, as they come at no cost to performance or area.For some circuits, over 10% power reduction can be achievedessentially for “free”.It is also interesting to look at the optimized power vs. theworst case don’t-care settings possible, as illustrated by therightmost bars in Figure 5 (vs. worst-case). In this experiment,we set the don’t-cares to the opposite of how they wouldnormally be set by our optimization algorithm, to examinethe potential worst-case glitch power arising from don’t-cares.Here, we see an average total dynamic power savings of 9.8%(a)(b)Fig. 5. (a) Dynamic power reduction vs. baseline (default) don’t-care settingsand worst-case settings. (b) Glitch power reduction vs. baseline (default)don’t-care settings and worst-case settings.and a peak savings of 30.8% (Figure 5(a)). These results showthat don’t-care settings can potentially have a large impact onpower if set to sub-optimal values.The varied results in Figure 5 can be correlated with theglitch power and don’t-care data in Tables II and III. Forinstance, des had a high glitch power in Table II, yet we did notobserve a significant power reduction for this circuit. However,in Table III, we see that it had only 0.8% of LUT inputsas don’t-cares, thus reducing the number of opportunities foroptimization. On the other hand, pdc had a high amount ofglitching as well as ample don’t-cares, thus allowing it to begreatly improved by the algorithm – 12.5% dynamic powerreduction.The relationship between don’t-cares, power and fanoutpresents a challenge to the glitch reduction algorithm. Fanoutis closely related to interconnect capacitance, and interconnectcan represent 60% of total FPGA dynamic power, on average[14]. Figure 6(a) shows logic signal power consumptionversus fanout, averaged across all signals in all circuits.Observe that, as expected, average signal power increases withfanout, due to the increase in capacitance. We also examined,for each signal, the fraction of minterms in its driving LUT thatwere don’t-cares, and averaged this across all signals of a givenfanout in all circuits. The results are shown in Figure 6(b).While the results are “noisy” for high fanout (due to a small

exists a highly preferable setting for a particular don’t-careminterm in a LUT. This is an important observation becauseit indicates that our don’t-care settings are providing a benefitmost of the time (as opposed to the case of a bias around 50%,which would imply that selecting either logic-0 or logic-1 forthe don’t-care minterm is equally good). These observationssuggest that one can pick don’t-care logic values with a highdegree of confidence.(a)(b)Fig. 6. (a) Power per signal vs. fanout. (b) Normalized don’t-cares per nodevs. fanout.Fig. 7.Average vote bias.sample size for such fanouts), we see that, in general, highfanout signals have fewer don’t-cares in their driving LUTsthan low fanout signals. The rationale for this is that highfanout signals are more likely to be used by at least one oftheir fanouts, decreasing ODCs for such signals. Essentially,we have two competing trends in that it is desirable to reducethe power of high fanout signals (as they consume significantpower), yet such signals exhibit fewer don’t-care opportunities.We also examined the bias of votes cast on each don’t-careminterm in each LUT in each circuit. The average results areshown in Figure 7. The bias is defined as the percentage ofvotes that were cast for the more popular setting, whetherlogic-0 or logic-1. As shown in the figure, the bias valuetends to be in the 80-100% range, indicating that there usuallyVI. CONCLUSION AND FUTURE WORKIn this paper, we presented an analysis of glitch power inFPGAs and a method for glitch reduction using don’t-cares inlogic synthesis. We showed that glitch power is a significantportion of total power, and that there exist ample opportunitiesfor don’t-care-based optimizations. A novel glitch reductiontechnique was presented that sets don’t-cares in FPGA configurationbits in order to avoid glitch transitions. This methodis performed after placement and routing, and has no effect oncircuit area or performance. The algorithm was evaluated witha commercial 65nm FPGA architecture using a commercialtool flow. The algorithm achieved an average total dynamicpower reduction of 4.0%, with a peak reduction of 12.5%;glitch power was reduced by up to 84%, and 13.7%, on average.Future work will involve integrating the algorithm into afully power-aware FPGA CAD flow, and investigating whetherother stages of the CAD flow could improve its effectiveness.For instance, the synthesis stage could be modified to createmore opportunities for this optimization.REFERENCES[1] Altera. Stratix III Device Handbook. http://www.altera.com/literature/lit-stx3.jsp.[2] Altera. Stratix V Device Handbook. http://www.altera.com/literature/lit-stratix-v.jsp.[3] L. Cheng, D. Chen, and M. Wong. GlitchMap: An FPGA technology mapper forlow power considering glitches. In ACM/IEEE DAC, pages 318 –323, 2007.[4] Tomasz S. Czajkowski and Stephen D. Brown. Using negative edge triggered FFsto reduce glitching power in FPGA circuits. In ACM/IEEE DAC, pages 324–329,2007.[5] Q. Dinh, D. Chen, and M. Wong. A routing approach to reduce glitches in lowpower FPGAs. In ACM ISPD, pages 99–106, 2009.[6] R. Fischer, K. Buchenrieder, and U. Nageldinger. Reducing the power consumptionof FPGAs through retiming. In IEEE Engineering of Computer-Based Systems,pages 89 – 94, 2005.[7] I. Kuon and J. Rose. Measuring the gap between FPGAs and ASICs. IEEE TCAD,26(2):203 –215, 2007.[8] J. Lamoureux, G. Lemieux, and S. Wilton. GlitchLess: Dynamic power minimizationin FPGAs through edge alignment and glitch filtering. IEEE TVLSI,16(11):1521 –1534, Nov. 2008.[9] H. Lim, K. Lee, Y. Cho, and N. Chang. Flip-flop insertion with shifted-phaseclocks for FPGA power reduction. In IEEE/ACM ICCAD, pages 335–342, 2005.[10] B. Lin and S. Devadas. Synthesis of hazard-free multilevel logic under multipleinputchanges from binary decision diagrams. IEEE TCAD, 14(8):974 –985, Aug1995.[11] A. Mishchenko and R. Brayton. SAT-based complete don’t-care computation fornetwork optimization. In ACM/IEEE DATE, pages 412–417, 2005.[12] A. Mishchenko, R. Brayton, J. Jiang, and S. Jang. Scalable don’t-care-based logicoptimization and resynthesis. In ACM FPGA, pages 151–160, 2009.[13] A. Mishchenko, S. Chatterjee, R. Brayton, and N. Een. Improvements tocombinational equivalence checking. In IEEE/ACM ICCAD, pages 836–843, 2006.[14] L. Shang, A. Kaviani, and K. Bathala. Dynamic power consumption in Virtex-IIFPGA family. In ACM FPGA, pages 157–164, 2002.[15] Berkeley Logic Synthesis and Verification Group. ABC: A system for sequentialsynthesis and verification, Release 00406. http://www.eecs.berkeley.edu/ ∼ alanmi/abc/.[16] S. Wilton, S. Ang, and W. Luk. The impact of pipelining on energy per operationin field-programmable gate arrays. In Proc. Intl. Conf. on FPL, pages 719–728,2004.[17] Xilinx. 7 Series FPGAs Overview. http://www.xilinx.com/support/documentation/7 series.htm.