serial communication controller (scc ™ sdlc mode of operation - Clips

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Application NoteSerial Communication Controller (SCC ): SDLC Mode of OperationRECEIVE INTERRUPTS ON FIRST CHARACTER OR SPECIAL CONDITIONSThe sequence of events in this mode is similar to that in“Receive Interrupts on all received characters and SpecialConditions”, except that it generates Receive CharacterInterrupt on the first received character only, andsubsequent data is read by the DMA.The SCC is placed in this mode by programming Bit D4-3of WR1 to 01. Once programmed in this mode, the SCCgenerates interrupts when it receives the First Character ofthe packet or a Special Condition occurs. This mode is foroperation with the DMA. On the interrupt for the firstreceived character, DMA is enabled. On SpecialConditions (either End-of-Message, overrun, or Parityerror, — parity on the SDLC is not normal, however), theservice routine stops the DMA and starts over again.RxCLKRx DataOpening Flag Data 81H Data 42H Data 0FFH Data 42H CRC 0E013H Closing FlagNote 9/INTNote 3➘Note 1Note 3Note 10Note 12➘➘Note 5Note 7➘Note 6Note 8➘➘➘➘/W//REQ (In /REQ mode)/SYNC➘➘Note 4Note 9➘Note 11➘Note 2Figure 3. Typical SDLC Receive Sequence with Receive Interrupts on First Character or Special Condition6-98
Application NoteSerial Communication Controller (SCC ): SDLC Mode of OperationNotes on Figure 3:1. The receiver is usually in hunt mode when waiting fora frame. When the opening flag is received, anExternal/Status Interrupt is generated, indicating thechange from hunt mode to sync mode.2. The /SYNC output follows the state of the sync registercomparison output. The comparison is done on a bitby bit basis, so the /SYNC pin is only active for one bittime./SYNC goes active one bit-time after the last bitof the sync character is sampled at the RxD pin.3. A Receive Character Available Interrupt is generated11 bit-times after the last bit of the character issampled at the RxD pin. In this mode, enable the DMAon this interrupt. This interrupt is for data 81H.4. If SCC’s DMA request function has been enabled,/REQ becomes active here.5. DMA request for data 42H.6. DMA request for data 0FFH.7. DMA request for data 42H.8. DMA request for the first CRC byte. The SCC treatsthe CRC as data, since the SCC does not yetdistinguish a difference between CRC and data!9. DMA request for the second CRC byte. The closingflag is recognized two bit-times before the secondCRC byte is completely assembled in the ReceiveShift Register. As soon as it is transferred to theReceive Buffer, it generates a DMA request.10. This interrupt is EOF (End of Frame), a SpecialCondition interrupt. This will not occur until the DMAhas read the 2nd CRC byte from the Receive Buffer.When it occurs, the Receive Buffer is locked and nomore DMA requests can be generated until theReceive Buffer is unlocked by issuing the Error Resetcommand. Before issuing this command, all of thestatus bits required (e.g., the CRC error status) mustbe read, and the last two bytes read by the DMAdiscarded. The enable interrupt on next ReceiveCharacter command must be sent to the SCC so thatthe next character (i.e., the First Character of the nextframe) will produce an interrupt. If this is not done, thecharacter will generate a DMA request, not aninterrupt.Should a Special Condition occur within the datastream (i.e., for a condition other than EOF) the /INTpin will not go active until the character with theSpecial Condition has been read by the DMA.11. DMA request for 2nd CRC bytes. This occurs whenthe EOF interrupt service routine has not disabled theDMA function of the SCC, and did not read the dataafter unlocking the buffer by issuing an Error Resetcommand.12. External/Status Interrupt for the Sync/Hunt change.This occurs when the SCC recognizes an Abort(Marking line) and forces the receiver into hunt mode.The SCC can be programmed so that the Abort itselfgenerates an interrupt if required. If flag idle was set,this interrupt would not occur.16-99
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serial communication controller (scc ™ sdlc mode of operation - Clips

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