(SRAM) IN HSPICE IKA DEWI BINTI SAIFUL BAHRI This thesis is ...

SIMULATION OF STATIC RANDOM ACCESS MEMORY (SRAM) IN HSPICEIKA DEWI BINTI SAIFUL BAHRIThis thesis is submitted in part of the requirement for the Degree of BachelorEngineering (Electrical-Microelectronics)Electrical Engineering FacultyUniversity of Technology MalaysiaJULY, 2012

ii“I declared that I have read through this thesis and my opinion this report is sufficientenough for fulfilling the standard of the thesis for the Bachelor Degree in ElectricalEngineering (Electrical-Microelectronics)”Signature : ………………………………………..Supervisor’s Name : DR. MICHAEL TAN LOONG PENGDate : 04 JULY 2012

iiiDECLARATION“I hereby declare that following project is the result of my own work expect forcommentaries and summaries that I had clearly stated the source”.Signature : ………………………………………Author : IKA DEWI BINTI SAIFUL BAHRII/C No : 880707-23-5064Date : 04 JULY 2012

ivDEDICATIONSpecial dedicated toMy lovely mother, Marlen Binti AgusMy dearest father, Saiful Bahri Bin MohdAnd all my family members and supportive friendsThanks for your full support

vACKNOWLEDGEMENTFirst of all, I would like to express my heartfelt thanks and highly appreciationto my respected supervisor, Dr Michael Tan Loong Peng for his assistances, invaluableadvices, encouragement, guidance, motivation and comments throughout this thesis.I also wish to convey my gratefulness to my beloved family for their love andsupport to succeed this thesis. Special thanks to all my friends and all whom had helpedand support me in one way or other during my project.

viABSTRACTNowadays, memory in one of the most important component in VLSI chip. It isused wisely in most micro-processor not only to store the data, but also needed to readand write the data. One type of the memories is called SRAM. In this thesis, a newmethod is suggested for simulate of Static Random Access Memory by using thePredictive Technology Model (PTM) card in HSPICE. This project is carried out toinvestigate the performance and the characteristics of the SRAM. The six transistorsSRAM cell is one of the most prevalent circuits in microelectronic design. The 6TSRAM cell is selected cell to be design in this project due to higher performance of thecell compared with the other type of cell. The objectives of this study are to design theSRAM cell by using the HSPICE software in three operations in the 6T SRAM cellswhich are in the normal, write and read operation.The operation time of each operation is observed and compared. The completetime taken for the read operation is higher than write operation. Static noise margin(SNM) in the write and read operation are calculated and discussed. SNM during readsimulation are greater than write operation. The smaller the static noise margins valuesthe better the design. The sizing of each MOSFET are really important in order to drivethe circuit achieved the maximum performance.

viiABSTRAKPada masa kini, memori di dalamsalah satukomponenyang palingpentingdalamcipVLSI. Ia digunakansecarabijakdalamkebanyakanpemprosesmikrobukansahajauntuk menyimpan data, tetapi jugadiperlukanuntukmembaca dan menulisdata.Satu jenismemori yangdipanggilSRAM. Dalam kajian ini,satukaedahramalanbarumencadangkanuntukmensimulasikanRandomAccessMemoryStatikdenganmenggunakanModelTeknologiramalan(PTM) kaddalam perisianpekej HSPICE.Model ramalanadalahproses di manamodeltelah ditubuhkan untukcubauntukmeramalkebarangkalianmemilihkeputusan. Projek inidijalankan untukmengetahuiprestasidanciri-ciri jenis SRAM. EnamtransistorSRAMselmerupakan salahsatudaripadalitaryang paling lazimdalam reka bentukmikroelektronik.SelSRAM6tdipilihselmenjadirekabentukdalam projek inikeranaprestasiyanglebihtinggiselberbandingdenganjenislaincel. Objektif kajianiniadalahuntuk mereka bentukselSRAMdengan menggunakanperisianpekejHSPICEdalam tigaoperasi disel6TSRAMyangbiasa, menulisdan membacaoperasi.Masaoperasisetiap operasidi kaji dan dibandingkan. Masayang lengkapuntukoperasimembacaadalahlebih tinggi daripadaoperasi tulis.Marginbunyistatik(SNM) untuk operasi menulisdan membacadikiradandibincangkan.SNMsemasasimulasimembacaadalahlebih besar daripadaoperasi tulis.Semakin kecilmarginbunyistatik semakin bagus reka bentuksesuatu litar.SaizsetiapMOSFETbenar-benarpentinguntukmemaculitarmencapaiprestasimaksimum.

viiiTABLE OF CONTENTSCHAPTER TITLEPAGEPAGE TITLEDECLARATIONDEDICATIONACKNOWLEDGEMENTABSTRACTABSTRAKTABLE OF CONTENTSLIST OF FIGURESLIST TABLELIST OF ABBREVIATIONiiiiiivviviiviiixixiiixiv1 INTRODUCTION1.1 Background 11.2 Problem Statement 21.3 Objective 41.4 Scope 5

ix2 LITERATURE REVIEW2.1 Introduction 62.2 HSPICE 72.3 CosmosScope 82.4 SRAM 92.4.1 Determine Cell (6T) 102.4.2 Static Noise Margin (SNM) 143 METHODOLOGY3.1 Introduction 163.2 Flow Chart 173.3 Circuit Modelling 183.4 Design in HSPICE 193.5 Simulation Work in CosmosScope 194 RESULT AND DISCUSSION4.1 Introduction 204.2 Inverter Simulation 214.2.2 Normal Operation Simulation 264.2.3 Read Operation Simulation 314.2.4 Write Operation Simulation 36

x5 CONCLUSIONS AND FUTURE WORK5.1 Conclusions 415.2 Future Work 436 REFERENCES 447 APPENDIX 46

xiLIST OF FIGURESFIGURES TITLE PAGE1.1 Previous project of SRAM cell 32.1 HSPICE integrator program 72.2 6T SRAM cell 102.3 A six transistor CMOS SRAM cell 122.4 SNM for an SRAM cell 143.1 Methodology 173.2 Structure sizing of transistor 183.3 Step of HSPICE design 194.1 Description of CMOS inverter 214.2 The input waveform of the inverter 234.3 The output waveform of the inverter 244.4 The input and output waveform of the inverter 254.5 6T SRAM cell netlist 264.6 SRAM simulation 284.7 HSPICE simulation for normal operation 304.8 Read modeling structure 314.9 Read operation netlist 324.10 Simulation in read operation 344.11 HSPICE simulation for read operation 354.12 Write operation modeling 36

xii4.13 Write operation netlist 374.14 Simulation in write operation 394.15 HSPICE simulation for write operation 40

xiiiLIST OF TABLESTABLE TITLE PAGE4.1 Graph description of normal operation 294.2 Transistor sizing 33

xivLIST OF ABBREVIATIONCMOS - Complementary Metal Oxide SemiconductorEDA - Electronic Design AutomationFET – Field-Effect TransistorGUI - Graphical User InterfaceIC - Integrated CircuitMOS – Metal-Oxide SemiconductorMOSFET – Metal-Oxide Semiconductor Field-Effect TransistorNMOS - n-channel Metal-Oxide SemiconductorPMOS - p-channel Metal-Oxide SemiconductorVLSI - Very Large Scale DeviceSNM – Static Noise Margin

CHAPTER 1INTRODUCTIONThis thesis investigates the performance of Static Random Access Memory(SRAM) in HISPICE simulation. 6T cell of SRAM is designed and the characteristic isobtained from the CosmosScope. In this chapter, the background of the project, problemstatement, project objectives, scope of work and the organization of the thesis arepresented.1.1 BackgroundPredictive Technology Model (PTM) provides accurate, customizable, andpredictive model files are compatible with the standard circuit simulators, such asSPICE, and scalable with a wide range of process variations. With PTM, competitivecircuit design and research can start even before the advanced semiconductortechnology is fully developed.

2SPICE is one of the types of Predictive Technology Model. There is a severaltype of SPICE such as TSPICE, PSPICE and the latest type is HSPICE. HSPICE isfaster and has more capabilities than typical SPICE simulators. More time can be savedand it easy to detect the error if there is the problem in simulation process.The Static Random Access Memory (SRAM) was created by using the HSPICEsoftware. The circuits performance of SRAM will be obtained through HSPICE and theperformance of circuit will be analyzed based on the waveform in generate fromCosmosScope.1.2 Problem StatementAccording to this project, some major improvements are made from the previousproject methodology. Initially, the previous projects use the typical SPICE simulatorwhich is more complicated and need more step and process to finish the project. Start itfrom design the schematic in S-Edit, proceed to draw the layout in L-Edit thencompared the net list in T-Spice. The problem will occur if both net lists are not sameand need to recheck the programmed from the start to solve the error.

3a) Schematic design b) Layout designFigure 1.1Previous project of SRAM cellThe major advantage by design the cell in HSPICE is faster and efficientcompared to other typical SPICE. The difference is HSPICE is that is no need to placethe schematic symbol onto the layout.

41.3 ObjectiveThere are two objectives in this project. The main objective is to predict theperformance of 16 bit SRAM using Predictive Technology Models (PTM) card. Thesepredictable models files are compatible with the standard circuit simulators, such asSPICE. The PTM model 32nm is one of PTM version for sub-45nm bulk CMOS. It isproviding new modeling features of metal gate/high-k, gate leakage, temperatureeffect, and body bias.Secondly, design circuit level modeling of SRAM in HSPICE.Generally thefewer transistors used the better the design. Cell size accounts for most of array size.Reduce cell size at expense of complexity. But the 1T and 3T cells are not types ofSRAM but DRAM. 6T cell SRAM had been choose as the cell SRAM in this project.

51.4 Scope of ProjectThis project consists of two phase; simulation and modeling. To study thecircuit-level modeling of SRAM which use HSPICE to design and simulate the netlistof 6T cell SRAMand CosmosScope to produce the output waveform to investigate thecharacteristic of 6T cell SRAM during the write and read operation. Secondly, studyon the characterization of the static random access memory and lastly, analyzing andinterpreting the data.

CHAPTER 2LITERATURE REVIEWThis chapter provides the background and reading of the project. These include adetail description of each device and operation that involved in this project.2.1 IntroductionThe software that will be used in order to simulate the Static Random Access Memory(SRAM) cell is HSPICE and CosmosScope. The netlists is designed in HSPICE and theoutput waveform will be generated by using CosmosScope. The simulation andinvestigation focused on 6T SRAM cell. Each bit in an SRAM is stored on fourtransistors that form two cross-coupled inverters. This storage cell has two stable stateswhich are used to denote “0” and “1”. Two additional access transistors help controllingthe access to the cross coupled unit formed by the inverters during read and writeoperations

72.2 HSPICEFigure 2.1HSPICE integrator programHSPICE simulator is one of the products from the HSPICE Integrator Program.It is able to generate the circuit in steady-state, frequency domains and also in thetransient state. Device reliability simulation and design yield process variability can bedone by using this program.One of the advantages of the HSPICE is can produce the very useful graphs thatcan design the project management and in engineering, which is graphical curves. Thissoftware uses the synopsis which the accurate gold standard for simulate the circuit andfully support the most accurate and expensive set of industry standard and proprietysimulation model. HSPICE precede the other program on both multicore and singlecomputers in term of the characterization application speed, extracted larger netlist,designing 65nm and integrity of signal.

82.3 CosmosScopeCosmosScope program can help HSPICE simulator to generate the outputwaveform. This is because CosmmosScope program can support the entire Synopsyssimulator. The data that are received from the other programme can be turn to the usefulinformation in CosmosScope. The advantages of the CosmosScope are:a. Measurement capabilities and powerful of analysis.b. Patented waveform-calculator technology.c. Scripting language based on the industry standard Tcl/Tkd. Can analyze the performance and quality of design; uparalleled capabilityand flexibilityThe result of the statistical circuit can be easy analysing by use CosmosScopesoftware. The different type of session of multiple output files generated can be simplyopen with the help of signal manager.Synopsys’ waveform calculator tool allows designers to further analysesimulation results. With most waveform-analysis products, each session must be startedfrom scratch, requiring valuable time searching for data files, rearranging windows, andso forth. CosmosScope, however, allows an entire session to be saved. Arrangements ofwindows, complete graphs, calculator contents and macros can be restored from aprevious session to continue work without interruption.After simulate, any number of graphs complete with annotations, text variables,and measurements can be saved. Then, in a later session, the graphs can be quicklyrestored for modification or for use as the basis for a new graph. CosmosScope alsoincorporates graph outlines that let designers apply axis-range labels, annotations, textvariables and measurements to new sets of waveforms; this allows definition of astandard template for subsequent sets of graphs and measurements.

92.4 SRAMThere is two type of RAM, first is SRAM and second is DRAM. Both of thisRAM is very important in computer system application. SRAM use a static method (aslong as the electric power is supplied to the memory chip, the data will remain constantand static) in order to stores the data. On the others hand, DRAM use the dynamicmethod, which is mean, it is always need to refresh the data stored in the memory.SRAM is faster and can save the use of power supply compared with DRAM.The structure of SRAM is more complex compared with DRAM. DRAM is lessexpensive to manufacture than SRAM. This reason SRAM is normally used in smallerapplication like CPU cache memory and user electronic and DRAM at all time used inlarger application like main memory for personal computers.The fewer transistors used and the smaller the cell the better the design. Due toincreasing of price of silicon wafer, using the smaller cell can reduce the total cost perbit of memory. The cell that used less that 3T is calling DRAM. The command cellused in SRAM is 6T. The structure of 6T SRAM cell is performing by 2 connectioninverter. The four transistors in the center form two cross-coupled inverters. In actualdevices, these transistors are made as small as possible to save chip-area, and are veryweak. Due to the feedback structure, a low input value on the first inverter will generatea high value on the second inverter, which amplifies (and stores) the low value on thesecond inverter. Similarly, a high input value on the first inverter will generate a lowinput value on the second inverter, which feeds back the low input value onto the firstinverter. Therefore, the two inverters will store their current logical value, whatevervalue that is.

102.4.1 Determine Cell (6T)Figure 2.2 below demonstrates the typical six-transistor cell used for CMOSstatic random-access memories (SRAM). The cell consists of two cross-coupled CMOSinverters that store one bit of information, and two N-type transistors that connect thecell to the bit lines.Figure 2.26T SRAM cellThe function of the logical gate inverter is to output the opposite of the input.This can be chained with other logic gates to allow for very complicate logic circuits.All logical circuits can be constructed out of OR and the invertors. A power inverter, onthe other hand, is a device that can be used to convert DC current to AC. This allows torun normal appliances (that require AC) off a battery (which delivers DC) or the like.An inverter is an electrical device that converts direct current (DC) to alternating

11current (AC); the resulting AC can be at any required voltage and frequency with theuse of appropriate transformers, switching, and control circuits. Inverters are commonlyused to supply AC power from DC sources such as solar panels or batteries.Static inverters have no moving parts and are used in a wide range ofapplications, from small switching power supplies in computers, to large electric utilityhigh-voltage direct current applications that transport bulk power.

12Figure 2.3A six transistor CMOS SRAM cellThere are three operations in SRAM simulation which is standby mode, readoperation mode and write operation mode. If the word line is not asserted, the accesstransistors M 5 and M 6 disconnect the cell from the bit lines. The two cross-coupledinverters formed by M 1 – M 4 will continue to reinforce each other as long as they areconnected to the supply. This operation is call standby operation.In the read operation, word line is activated while the external word line driveris disabled. The value can be determined by external logic if the inverter inside theSRAM cell drives the bitlines.In the write operation, in order to drive the bitlines, the big (external) tristatedrivers need to activate first. The previous state of the cross-couple can easily beoverride. It is because the internal driver (small transistor used in the 6T SRAM cell) ismuch smaller than the external drivers. Next, allowed the wordline transistors. Still,when shafting the data, the short-circuit will happen for just a few nanoseconds.

13So typically it takes six transistors to store one memory bit. The design of abasic SRAM cell is shown in Figure 2.3. Access to the cell is enabled by the word line(WL) which controls the two access transistors M5 and M6 which allow the access ofthe memory cell to the bit lines: ‘BL’ and ‘BLbar’. They are used to transfer data forboth read and write operations. The presence of dual bit lines i.e. ‘BL’ and ‘BLbar’improves noise margins over a single bit line. The operation of CNFETs basedmemories is very similar to that of CMOS except for minor differences in deviceorientation. One such difference being that the source and drain terminals of a CNFETare not interchangeable as is the case with CMOS devices. Care must therefore be takento orient the transistors in a memory cell in a manner that will ensure correcttransmission of logic levels.

142.4.2 Static Noise Margin (SNM)Static noise margin (SNM) is the maximum voltage amplitude of external signalthat can be algebraically added to the noise-free worst-case input level without causingthe output voltage to diverge from the allowable logic voltage level. SNM is the mostimportant parameters of SRAM cell because too compared which cell is better and asDC disturbance present in logic gates. The concept of SNM for an SRAM cell is shownthe figure below.Figure 2.4SNM for an SRAM cell

15The minimum noise voltage to flip the state of the cell at each of the cell storageis called SNM. SNM can be obtained by drawing and mirroring the invertercharacteristics (left side and right side inverter of the 6T cell). Next, determine themaximum square between both inverters.

CHAPTER 3METHODOLOGY3.1 IntroductionThis chapter discusses the methodology and step that involved in this project.This project implicates programming simulation and design only. This chapter alsoexplains the flow of the project step and the software involves in this project.

173.2 Flow ChartFigure 3.1shows the flow chart of this project. The first stage is literature reviewon HSPICE and CosmoScope software and SRAM chip in general and 6T cell SRAMstructure in particular. All of the information that collected from the web site, relatedbooks and from my supervisor need to be understood thoroughly.Literature review on Hspice, CosmosScope andSRAMCircuit modellingDesign in HspiceSimulation in CosmosScopeFigure 3.1Methodology

183.3 Circuit ModelingThere are 3 types of model that need to be design in this project which start fromthe normal operation of SRAM cell then followed by the write operation and readoperation. The pull-up PMOS transistors is sized as twice or three-times the widths ofthe pull-down NMOS transistors. It is because the mobility of PMOS is less than twiceor three time than the NMOS transistors. The size of both access transistor need to begreater than the PMOS MOSFET and smaller than the NMOS MOSFET to achievehigher design performance.Figure 3.2Structure sizing of transistor

193.4 HSPICE DESIGNAll 6 transistors and Word Line (WL), Bitline (BL) and BLB (BLB) are labeledcorrectly. Node Q and QB are label in order to simply the process of design the netlistin the HSPICE later. There are four processes in this step.Inverter NetlistSRAM cell netlistWrite and read operation netlistFigure 3.3Step of HSPICE design3.5 Simulation Work in CosmosScopeRecalling that, HSPICE is used for circuit simulation and CosmosScope is usedto view output waveform. The simulation work of SRAM will be discussed more deeplyin the result and discussion part later. Time analysis and the characteristic of SRAMwill be diagnosed.

CHAPTER 4RESULT AND DISCUSSION4.1 IntroductionThis chapter discusses the simulation of output waveform generated inCosmosScope. It is divided into the four parts; inverter simulations, normal simulation,write operation and read operation

214.2 Inverter SimulationSince the 6T SRAM are formed by combination of two inverter, theunderstanding of this project will start with the inverter net list first.HSPICE is used for circuit simulation and CosmosScope is used to viewoutput waveform. 6T SRAM cell are form of two combination inverter. Figure4.1 show the description of CMOS inverter..lib “tsmc_018nm_model.txt” cmos_modelM1 out in vdd vdd pmos L=0.18n W=1.8nM2 out in 0 0 nmos L=0.18n W=0.9nVdd Vdd 0 2.5Vin in 0 0 pulaw 0 2.5 200p 200p 200p 5n 10nCload out 0 20f.options post.tran 200p 20n.print tran v(in) v (out).endFigure 4.1Description of CMOS inverterThe first line of the SPICE file is always a comment line. Therefore anystatements on this line will be ignored. The .lib line includes the model file32n.txt, which is assumed to be in the current running directory. The next twolines are a PMOS and an NMOS transistor, respectively. After the transistorname (which must begin with m), the source, gate, drain, and bulk nodes aregiven.

22Next is the model. The length and width are specified. The process is a0.18um process, so 0.18um is the minimum gate length. Source and drainperimeters and areas can also be specified here. The two supply nets are definednext.A pulse voltage source is defined from 0 to 2.5 V with 100ps delay,100ps rise time, 100ps fall time, 2n pulse width, and 4ns repetition period. Acapacitor of 20fF from node out to node 0 is given on the next line. .options postinstructs HSPICE to write an output file ending in .tr0 containing the simulationwaveforms. .tran indicates a transient analysis with a plot interval of 200ps andsimulation duration of 20ns. .print specifies the nodes to be printed to the .outfile. .end signifies the end of the SPICE stack. This command runs HSPICE onthis file: hspiceinv.cir>inv.out.

23Several files are created by HSPICE: inv.ic: Text file containing thecircuit initial conditions inv.st0: Text files containing a summary of thesimulation inv.tr0: Binary files containing transient analysis waveforms.Figure 4.2Theinput waveform of the inverter

24After the simulation, the waveforms can be viewed using CosmosScope.A signal manager window and the Plot File window will open up. In the PlotFilewindow, plot v(in) by double clicking v(in), or by selecting v(in) andclicking Plot. Theinput waveform of the inverter will open up. Then, plot v(out),the same way as plotted v(in). This will open another graph with v(out).Figure 4.3Theoutput waveform of the inverter

25Then compare the input and ouput on the same graph, simply click anddrag the title “v(out)” from the top graph to the bottom graph where v(in) isplotted.Figure 4.4The input and output waveform of the inverter

264.3 Normal SimulationAs mentioned before, by depending on the transistor label and node name inFigure 3.2, the netlist of SRAM will be designed in HSPICE.SRAM cell 6T.lib "32n.txt" cmos_models*source**supplyvdd 4 0 dc 2**access controlvwl wl 0 pulse(0 4 100u 100u 2m 8m)**datavbl bl1 0 dc 1vblr blr1 0 pulse(0 1 5m 100u 100u 15m 1)**controlvr_w r_w 0 pulse(0 1 0 1u 1u 10m 1)*devices**switchesGBL BL1 BL VCR PWL(1) r_w,0 0,1e20 1m,1e-20GBLR BLR1 BLR VCR PWL(1) r_w,0 0,1e20 1m,1e-20**mos transistors - latchm1 Q QR 0 0 nmos W=88n L=22nm2 Q QR 1 1 pmos W=33n L=33nm3 QR Q 0 0 nmos W=88n L=22nm4 QR Q 1 1 pmos W=33n L=33n**mos transistors - data accessm5 BL wl Q 1 nmos W=44n L=22nm6 BLR wl QR 1 nmos W=44n L=22n*analysis.tran 1u 45m 0.option post.endFigure 4.56T SRAM cell netlist

27As explained in the inverter simulation, the first line of the SPICE file isalways a comment line. Therefore any statements on this line will be ignored.The .lib line includes the model file 32n.txt, which is assumed to be in thecurrent running directory. As a access controller, a pulse of wordline (WL)source is defined from 0 to 4 V with 100 micro second rise time, 100 microsecond fall time, 2ms pulse width, and 8ms repetition period. As a datacontroller, pulse voltage of bitline (BL) source is defined from 0 to 1 V with5ms delay, 100 micro second rise time, 100 micro second fall time, 15m pulsewidth, and 1 repetition period. . As a controller, a write pulse voltage source isdefined from 0 to 1 V with 0s delay, 100 micro second rise time, 1 micro secondfall time, 10ms pulse width, and 1 repetition period.The command .options” post instructs HSPICE to write an output fileending in .tr0 containing the simulation waveforms. .tran indicates a transientanalysis with a plot interval of 1micro second and simulation duration of 45 ms..end signifies the end of the SPICE stack. This command runs HSPICE on thisfile: hspiceinv.cir>inv.out

28Figure 4.6SRAM simulation

29The Figure 4.1 shows the simulation of SRAM 6T cell. From the Figure 2.2 theoutput voltage at node Q is depending on WL and BL input. Once the WL and BL aresupply with input and voltage at node Q will start to increase, otherwise it will remainzero. On the other hand, the output voltage at node QB is depending on WL and BLB.WL control both side of inverter.V (WL)V(r_w)V(qr)V(q)V(bl)V(blr)I(vr_w)i(vdd)i(vblr)i(vbl)Table 4.1Graph descriptionWorldline voltageWrite voltageVoltage at node QRVoltage at node QBitline voltageBitline Bar voltageWrite currentVoltage supply currentBitline bar currentBitline current

30Figure 4.7HSPICE simulationFigure 4.6 show the total MOSFET used is six; two PMOS MOSFET and fourNMOS MOSFET. The transient time is 0.10 second and the circuit took 0.20 seconds tocomplete the simulation. This figure will only show when there is no error occur duringthe simulation

314.4 Read Operation SimulationThe wordline (WL) and bitlines (BL) are held at V DD during read operation.Figure 4.8 shows how to extract the read static noise margin (SNM) of the cell.Figure 4.8 Read modeling structureFirst, the feedback from the cross coupled inverters is broken. Next, the voltageof the inverter formed by half of the SRAM cell is found by sweeping Q (the inverter’sinput) from 0 to V DD and measuring QB (the inverter’s output). This plot is then used toconstruct the “butterfly plot” that is representative of the two halves of the cell drivingeach other. The read SNM is the side length of the maximum possible square that can fitinside of the butterfly plot.

32SRAM cell read 6T*6Transistor SRAM.TEMP 25.0000.lib "32n.txt" cmos_models.PARAM VDD= 0.95.PARAM VNOISE = 0.66.PARAM BITCAP = 1e-12.OPTION POSTCBL BLB 0 BITCAPCBLB BL 0 BITCAP*one inverterMPL Q QBN VDD! VDD! pmos L=33n W=33nMNL Q QBN 0 0 nmos L=22n W=88n*one inverterMPR QB QN VDD! VDD! pmos L=33n W=33nMNR QB QN 0 0 nmos L=22n W=88n*access transistorMNAL BLB WL QB 0 nmos L=22n W=44nMNAR BL WL Q 0 nmos L=22n W=44nVVDD! VDD!0 DC=VDDVWL WL 0 DC=VDDVNOISEL QBN QB DC=VNOISEVNOISER Q QN DC=VNOISE*logic 1 is stored in the cell initially.IC V(Q)=VDD.IC V(QB)=0*writing logic 0 in cell.IC V(BL)=VDD.IC V(BLB)=VDD.TRAN 0.1n 30n.PRINT TRAN V(QB) V(Q) V(BLB) V(BL).ENDFigure 4.9Read operation netlistThe V DD supply was set to 0.95 V. The HSPICE simulator will give error if thevoltage is less than 0.25 V. It is happen because, the supply voltage need to be higherthan threshold voltage. Set the input for V(Q)= V DD and V(QB)=0 to store the logic “1”in the cell initially. Write the logic “0” in the cell by set the V(BL)= V DD and V(BLB)=V DD .

33Voltage VNOISE is used to control the cell flipping of the output. It can be setinto any required number and did some investigation, VNOISE= 0.66 volt is the valuefor this simulation project. Broken up the cell inside the 6T SRAM into the two parts.Each part acts as inverter. Length of transistor is set as Figure 3.2.Table 4.2 Transistor sizingLength(L) Weight(W)Pull-up 33n 33nPull-down 22n 88nPass gate 22n 44n

34Figure 4.10 Simulation in read operationA. SNM in read operation B. Simulation in the right inverter.C. Simulation in the left inverterDuring the read operation, when QB reaches the threshold voltage of theNMOS, M3, the voltage at node Q starts to fall and the regenerative action of the crosscoupledinverter will force the flipping on the bit in the cell. To prevent the readoperation failure the values of M5 should be strong enough to make sure the stability ofthe operation can be achieved. The SNM value of the write operation is 0.1016V. Thetotal time to complete this operation is 0.22s

35Figure 4.11HSPICE simulationSince, Figure 4.11shows the total MOSFET used in read simulation is six, itmeans there is no missing transistor in this simulation. The HSPICE simulationcalculates it correct and no error occur. The transient time is 0.08 second and the circuittook 0.22 seconds to complete the simulation.

364.5 Write Operation SimulationDuring a write operation, V DD is applied to the wordline and the value to bewritten into the memory cell is driven onto the bitlines. Thus, Figure 3.4 illustrates howto extract the write static noise margin (SNM). Again, feedback from the cross-coupledinverters is broken and the voltage of the inverter is measured. Note however that in thiscase, the voltages of the two halves of the SRAM are no longer the same (since one thebitlines is driven to 0V, and the other to V DD ). These voltages are used to create abutterfly plot, and write SNM is the side length of the largest that can fit inside of thebutterfly plot.Figure 4.12Write operation modeling

37*6Transistor SRAM.TEMP 25.0000.lib "32n.txt" cmos_models.GLOBAL VDD!.PARAM VDD = 0.95.PARAM VNOISE = 0.66.PARAM BITCAP = 1e-12.OPTION POSTCBL BLB 0 BITCAPCBLB BL 0 BITCAP*one inverterMPL Q QBN VDD! VDD! pmos L=32n W=32nMNL Q QBN 0 0 nmos L=56n W=32n*one inverterMPR QB QN VDD! VDD! pmos L=32n W=32nMNR QB QN 0 0 nmos L=56n W=32n*access transistorMNAL BLB WL QB 0 nmos L=38n W=37nMNAR BL WL Q 0 nmos L=38n W=37nVVDD! VDD!0 DC=VDDVWL WL 0 DC=VDDVNOISEL QBN QB DC=VNOISEVNOISER Q QN DC=VNOISE*logic 1 is stored in the cell initially.IC V(Q)=VDD.IC V(QB)=0*writing logic 0 in cell.IC V(BL)=0.IC V(BLB)=VDD.TRAN 0.1n 30n UIC.PRINT TRAN V(QB) V(Q) V(BLB) V(BL).ENDFigure 4.13 Write Operation netlist

38Same as read operation, the V DD supply in write operation was set to 0.95 V.The HSPICE simulator will give error if supply voltage is less than threshold voltage.Set the input for V(Q)= V DD and V(QB)=0 to store the logic “1” in the cell initially.Supply the logic “0” to the bitline voltage by set the V(BL)= 0. Then give the value “1”to the beltline bar, V(BLB)= V DD . The others values are same with the read operation.Sizing of each transistor are set as table 4.1.

39Figure 4.14Simulation in write operationA. SNM in the write operation B. Simulation in the right inverter.C. Simulation in the left inverterDuring the write operation, write Q=0 while Q= V DD. When the voltage at nodeQ reaches a voltage so that the PMOS, M2, gets on, the voltage at note QB starts to riseand the regenerative action of the cross-coupled inverter will force the write Q=0. Toprevent the write operation failure the values of M6 should be strong enough to makesure the stability of the operation can be achieved. The SNM value of the writeoperation is 0.051792V. The total time to complete this operation is 0.09s

40Figure 4.15 HSPICE simulationSame as read operation, since, Figure 4.15shows the total MOSFET used in readsimulation is six; it means there is no missing transistor in this simulation. The HSPICEsimulation calculates it correct and no error occur. The transient time is 0.05 second andthe circuit took 0.09 seconds to complete the simulation.

CHAPTER 5CONCLUSIONS AND FUTURE WORK5.1 ConclusionsAs a conclusion, this PTM model which is using HSPICE software andproduced the output in CosmosScope is more efficient compare to typical Spice. Thecircuit performance of SRAM will be obtained through HSPICE software simulationusing PTM. The performance of each devices and circuit will be analysed based on thewaveform in generated from CosmosScope such as a Static Noise Margin (SNM). Staticnoise margin is the DC disturbance present in logic gates. It is the most importantparameters of an SRAM cell. Can be determines by nesting the largest possible squarein the 2 voltage transfer curve of the CMOS inverters. The SNM defines as the sidelengthof the square, given in volts. The SNM are determined to compared the whichoperation is better. It is importance to use the exact transistor size in order to make surethat the cell working and running with the maximum performance. The predictionmodel is almost same, but not accurate due to the problem of finding the exact values oftransistor used.

42The SNM values of the read operation were higher than write operation. Theread static-noise-margin (SNM) deteriorates with decrease in supply voltage (V DD ) andincreases with the transistor mismatch. This mismatch happens due to variations inphysical quantities of identically designed devices i.e., their threshold voltages, bodyfactor and current factor. Though SNM decreases at low V DD the overall SRAM delayincreases and moreover the read operation at low V DD leads to storage data destructionin SRAM cells. The main operations of the SRAM cell are the write, read and hold. Thestatic noise margin is certainly more important at hold and read operations. Specificallyin read operation when the wordline is „1‟ and the bitlines are precharged to “1”. Theinternal node of SRAM which stores “0” will be pulled up through the access transistoracross the access transistor and the driver transistor. This increase in voltage severelydegrades the SNM during read operation. The SNM deteriorates with the decrease insupply voltage, at low V DD the read and write operations cannot perform properly. Thecomplete time for write operation is greater than the read operation because during readoperation, the cell need to wait the input from the outside to start operate, but in thewrite operation the input is already store in the cell.

435.2 Future workRegarding of the limited scope of this project, it is possible to chase allrequirement to a final better conclusion. To improve the project, the followingsuggestion should be carried out.a. The used of voltage VNOISE is to control and check the output cell flipping.In order to get the exact values of VNOISE, graphical technique can be used.The polarity of the noise voltage sources at the input of each inverter. Itdepends on the logic values of the bit stored in the cell.b. The cell ration (ratio of the widths of pull-down NMOS and accesstransistor) for read and pull-up ratio (ratio of the width of pull-up PMOS andaccess transistor) for write can be determine first in order the get the exactvalue of transistors by using hand calculation.

44REFERENCES[1] http://www.ee.vt.edu/~ha/cadtools/hsp ice/hspice.html,HSPICE andCosmosScope tutorial[2] HSPICE RF Tutorial, Version X, 2005[3] L. Chang et al, “Stable SRAM Cell Design for the 32nm Node and Beyond,”Symp.VLSI Tech, Dig, pp. 292-293, Jun, 2005.[4] Neil H. Weste, David Harris,"CMOS VLSI Design," 3rd edition, Chapter 11,Addison Wesley 2005[5] K. Takeda et al, “A Read-Static-Noise-Margin-Free SRAM Cell for Low-Vdd andHigh-Speed Application,” IEEE JSSC, pp, 113-121, Jan 2006.[6]E. Seevinck et al “Static-Noise Margin Analysis of MOS SRAM Cells, “ IEEEJSSC, pp 748-754, Oct 1987.[7]Mo Maggie Zhang, “Performance Comparison of SRAM Cells Implemented in 6,7,and 8-Transistor Cell Topologies”, IEEE, 2000[8] W.Zhao and Y.Cao, “New Generation of Predictive Technology Model for Sub-45nm Early Design Exploration (Journal), IEEE Transaction on Electron Devices,Nov. 2006- 11: Vol.50[9]http://en.wikipedia.org/wifi/SRAM[10] Yasuhiro Marita, HidehiroFujiwira, Hiroki Noguchi, Yusuke Iguchi, Koji Nii,Hirochi Kawaguchi, Masahiko Yoshimoto. “Area comparison between 6T and 8TSRAM Cells in Dual-Vdd Scheme and DVS Scheme”, Trans. Fundamentaos,Vol.E90-A, No12 December 2007[11] S. R. Nassif, “Modeling and analysis of manufacturing variations,” in Proceedingsof the IEEEConference on Custom Integrated Circuits, pp. 223–228, 2001.

45[12] M. Orshansky, S. Nassif, and D. Boning, Design for manufacturability andstatistical design. Springer Publications, P.O.Box 17, 3300 AA Dordrecht, TheNetherlands, 2007.[13]. S. Nassif, “Delay variability: sources, impacts and trends,” in Proceedings of theIEEE International Solid-State Circuits Conference, pp. 368– 369, 2000.[14] E. Grossar, M. Stucchi and K. Maex, “Read Stability and Write-Ability Analysis ofSRAM Cells for Nanometer Technologies”, IEEE Journal of Solid-State Circuits,41(11) (2006), pp. 2577-2588.[15] S. Verhaegen, S. Cosemans, M. Dusa, P. Marchal, A. Nackaerts, G. VandenbergheandW. Dehaene, “Litho Variations and Their Impact on the Electrical Yield of a32nm Node 6T SRAM Cell”, Proc. SPIE Design for ManufacturabilitythroughDesign-Process Integration II, 6925 (2008), pp. 69250R-1–69250R-12.[16] J. Wang and A. K. Wong, “Effects of Grid-Placed Contacts on CircuitPerformance”, Proc. SPIE Cost and Performancein Integrated Circuit Creation,5043 (2003), pp. 134-141.[17]L. Chang et al., “Stable SRAM Cell Design for the 32nm Node and Beyond,”Symp. VLSI Tech. Dig., pp. 292-293, Jun., 2005.[18] K. Takeda et al., “A Read-Static-Noise-Margin-Free SRAM Cell for Low-Vdd andHigh-Speed Applications,” IEEE JSSC, pp. 113-121, Jan., 2006.[18] E. Seevinck et al., “Static-Noise Margin Analysis of MOS SRAM Cells,” IEEEJSSC, pp.748-754, Oct.1987.[19] J. Wang, A. K. Wong and E. Y. Lama, “Standard Cell Design with Regularly-Placed Contacts and Gates”, Proc.SPIE Design and Process Integration forMicroelectronic Manufacturing, 5379 (2005), pp. 56-66.[20] A. Bhavnagarwala, et al., “A Transregional CMOS SRAM with Single, LogicVDD and Dynamic Power Rails, Symp.on VLSI Circuits, 2004.[21] H. Qin, et al., “SRAM Leakage Supressiong by Minimizing Standby SupplyVoltage,” ISQED, 2004.[22] K. Takeuchi, R. Koh, and T. Mogami, "A Study of the Threshold VoltageVariation for Ultra-Small Bulk andSOI CMOS," IEEE Transactions on ElectronDevices, Vol. 48, No. 9, September 2001

46APPENDIX32 PTM Model* PTM 32nm Metal Gate / High-K.lib cmos_models.model nmos nmos level = 54+version = 4.0 binunit = 1 paramchk= 1 mobmod = 0+capmod = 2 igcmod = 1 igbmod = 1 geomod = 1+diomod = 1 rdsmod = 0 rbodymod= 1 rgatemod= 1+permod = 1 acnqsmod= 0 trnqsmod= 0+tnom = 27 toxe = 7.5e-010 toxp = 5e-010 toxm = 7.5e-010+dtox = 2.5e-010 epsrox = 3.9 wint = 5e-009 lint = 1.95e-009+ll = 0 wl = 0 lln = 1 wln = 1+lw = 0 ww = 0 lwn = 1 wwn = 1+lwl = 0 wwl = 0 xpart = 0 toxref = 7.5e-010 xl= -14e-9+dlcig = 1.95e-009+vth0 = 0.3558 k1 = 0.2 k2 = 0 k3 = 0+k3b = 0 w0 = 2.5e-006 dvt0 = 1 dvt1 = 2+dvt2 = 0 dvt0w = 0 dvt1w = 0 dvt2w = 0+dsub = 0.078 minv = 0.05 voffl = 0 dvtp0 = 1e-011+dvtp1 = 0.1 lpe0 = 0 lpeb = 0 xj = 1e-008+ngate = 1e+023 ndep = 8.7e+018 nsd = 2e+020 phin = 0+cdsc = 0 cdscb = 0 cdscd = 0 cit = 0+voff = -0.13 nfactor = 2.1 eta0 = 0.005 etab = 0+vfb = -1.058 u0 = 0.0238 ua = -5e-010 ub = 1.7e-018+uc = 0 vsat = 182130 a0 = 1 ags = 0+a1 = 0 a2 = 1 b0 = 0 b1 = 0+keta = 0.04 dwg = 0 dwb = 0 pclm = 0.06+pdiblc1 = 0.001 pdiblc2 = 0.001 pdiblcb = -0.005 drout = 0.5+pvag = 1e-020 delta = 0.01 pscbe1 = 2.0e+009 pscbe2 = 1e-007+fprout = 0.2 pdits = 0.01 pditsd = 0.23 pditsl = 2300000+rsh = 5 rdsw = 80 rsw = 40 rdw = 40+rdswmin = 0 rdwmin = 0 rswmin = 0 prwg = 0+prwb = 0 wr = 1 alpha0 = 0.074 alpha1 = 0.005+beta0 = 30 agidl = 0.0002 bgidl = 2.1e+009 cgidl = 0.0002

47+egidl = 0.8 aigbacc = 0.012 bigbacc = 0.0028 cigbacc = 0.002+nigbacc = 1 aigbinv = 0.014 bigbinv = 0.004 cigbinv = 0.004+eigbinv = 1.1 nigbinv = 3 aigc = 0.020014 bigc = 0.0027432+cigc = 0.002 aigsd = 0.020014 bigsd = 0.0027432 cigsd = 0.002+nigc = 1 poxedge = 1 pigcd = 1 ntox = 1+xrcrg1 = 12 xrcrg2 = 5+cgso = 9e-011 cgdo = 9e-011 cgbo = 0 cgdl = 7.5e-013+cgsl = 7.5e-013 clc = 1e-007 cle = 0.6 cf = 1.1e-010+ckappas = 0.6 ckappad = 0.6 vfbcv = -1 acde = 1+moin = 15 noff = 1 voffcv = 0+kt1 = -0.154 kt1l = 0 kt2 = 0.022 ute = -1.1+ua1 = 1e-009 ub1 = -1e-018 uc1 = -5.6e-011 prt = 0+at = 33000+fnoimod = 1 tnoimod = 0 noia = 6.25e+041 noib =3.125e+026+noic = 8.75e+009 em = 41000000 af = 1 ef = 1+kf = 0 tnoia = 1.5 tnoib = 3.5 ntnoi = 1+jss = 1.2e-006 jsws = 2.4e-013 jswgs = 2.4e-013 njs = 1+ijthsfwd= 0.1 ijthsrev= 0.1 bvs = 10 xjbvs = 1+jsd = 1.2e-006 jswd = 2.4e-013 jswgd = 2.4e-013 xjbvd = 1+pbs = 1 cjs = 0.0018 mjs = 0.5 pbsws = 1+cjsws = 1.2e-010 mjsws = 0.33 cjswgs = 2.1e-010 cjd = 0.0018+cjswd = 1.2e-010 mjswd = 0.33 pbswgd = 1 cjswgd = 2.1e-010+mjswgd = 0.33 tpb = 0 tcj = 0 tpbsw = 0+tcjsw = 0 tpbswg = 0 tcjswg = 0 xtis = 3+dmcg = 0 dmci = 0 dmdg = 0 dmcgt = 0+dwj = 0 xgw = 0 xgl = 0+rshg = 0.4 gbmin = 1e-010 rbpb = 5 rbpd = 15+rbps = 15 rbdb = 15 rbsb = 15 ngcon = 1.model pmos pmos level = 54+version = 4.0 binunit = 1 paramchk= 1 mobmod = 0+capmod = 2 igcmod = 1 igbmod = 1 geomod = 1+diomod = 1 rdsmod = 0 rbodymod= 1 rgatemod= 1+permod = 1 acnqsmod= 0 trnqsmod= 0+tnom = 27 toxe = 7.7e-010 toxp = 5e-010 toxm = 7.7e-010+dtox = 2.7e-010 epsrox = 3.9 wint = 5e-009 lint = 1.95e-009+ll = 0 wl = 0 lln = 1 wln = 1

48+lw = 0 ww = 0 lwn = 1 wwn = 1+lwl = 0 wwl = 0 xpart = 0 toxref = 7.7e-010 xl= -14e-9+dlcig = 1.95e-009+vth0 = -0.24123 k1 = 0.2 k2 = -0.01 k3 = 0+k3b = 0 w0 = 2.5e-006 dvt0 = 1 dvt1 = 2+dvt2 = -0.032 dvt0w = 0 dvt1w = 0 dvt2w = 0+dsub = 0.1 minv = 0.05 voffl = 0 dvtp0 = 1e-011+dvtp1 = 0.05 lpe0 = 0 lpeb = 0 xj = 1.008e-008+ngate = 1e+023 ndep = 3.5e+018 nsd = 2e+020 phin = 0+cdsc = 0 cdscb = 0 cdscd = 0 cit = 0+voff = -0.13 nfactor = 2.1 eta0 = 0.0042 etab = 0+vfb = -1.058 u0 = 0.00306 ua = -5e-010 ub = 1.6e-018+uc = 0 vsat = 78000 a0 = 1 ags = 1e-020+a1 = 0 a2 = 1 b0 = 0 b1 = 0+keta = -0.047 dwg = 0 dwb = 0 pclm = 0.1+pdiblc1 = 0.001 pdiblc2 = 0.001 pdiblcb = 3.4e-008 drout = 0.6+pvag = 1e-020 delta = 0.01 pscbe1 = 2e+009 pscbe2 = 9.58e-007+fprout = 0.2 pdits = 0.08 pditsd = 0.23 pditsl = 2300000+rsh = 5 rdsw = 80 rsw = 40 rdw = 40+rdswmin = 0 rdwmin = 0 rswmin = 0 prwg = 0+prwb = 0 wr = 1 alpha0 = 0.074 alpha1 = 0.005+beta0 = 30 agidl = 0.0002 bgidl = 2.1e+009 cgidl = 0.0002+egidl = 0.8 aigbacc = 0.012 bigbacc = 0.0028 cigbacc = 0.002+nigbacc = 1 aigbinv = 0.014 bigbinv = 0.004 cigbinv = 0.004+eigbinv = 1.1 nigbinv = 3 aigc = 0.011942 bigc = 0.0012217+cigc = 0.0008 aigsd = 0.011942 bigsd = 0.0012217 cigsd = 0.0008+nigc = 1 poxedge = 1 pigcd = 1 ntox = 1+xrcrg1 = 12 xrcrg2 = 5+cgso = 9e-011 cgdo = 9e-011 cgbo = 0 cgdl = 3e-011+cgsl = 3e-011 clc = 1e-007 cle = 0.6 cf = 1.1e-010+ckappas = 0.6 ckappad = 0.6 vfbcv = -1 acde = 1+moin = 15 noff = 1 voffcv = 0+kt1 = -0.14 kt1l = 0 kt2 = 0.022 ute = -1.1+ua1 = 1e-009 ub1 = -1e-018 uc1 = -5.6e-011 prt = 0+at = 33000+fnoimod = 1 tnoimod = 0 noia = 6.25e+041 noib =3.125e+026+noic = 8.75e+009 em = 41000000 af = 1 ef = 1+kf = 0 tnoia = 1.5 tnoib = 3.5 ntnoi = 1

49+jss = 2e-007 jsws = 4e-013 jswgs = 4e-013 njs = 1+ijthsfwd= 0.1 ijthsrev= 0.1 bvs = 10 xjbvs = 1+jsd = 2e-007 jswd = 4e-013 jswgd = 4e-013 xjbvd = 1+pbs = 1 cjs = 0.0015 mjs = 0.5 pbsws = 1+cjsws = 9.4e-011 mjsws = 0.33 cjswgs = 2e-010 cjd = 0.0015+cjswd = 9.4e-011 mjswd = 0.33 pbswgd = 1 cjswgd = 2e-010+mjswgd = 0.33 tpb = 0 tcj = 0 tpbsw = 0+tcjsw = 0 tpbswg = 0 tcjswg = 0 xtis = 3+dmcg = 0 dmdg = 0 dmcgt = 0 xgw = 0+xgl = 0+rshg = 0.1 gbmin = 1e-012 rbpb = 50 rbpd = 50+rbps = 50 rbdb = 50 rbsb = 50 ngcon = 1