GDR SoC SiP

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Memory PUFMore details given in the Talk of VincentVan der Leest from INTRINSIC-ID Principle• Convergence towards a steady state from anunstable state : Metastable Power onWhat happens whenReset goes to ‘0’ ?Su Y., Holleman J., Otis B.: “A 1.6pj/bit 96% stable chip-id generating circuit using process variations”. In:. ISSCC 2007. Digest ofTechnical Papers. IEEE, pp. 406-611, 2007page 10Télécom ParisTechGDR SoC SiP
Memory PUF Pros• Good uniqueness• Implementable in any technology with Non initialized SRAM DFF, latches Bus keepers• No ML attack Cons• Few challenges• Sensitive to noise and environmentpage 11Télécom ParisTechGDR SoC SiP
Page 1 and 2: GDR SoC SiPPUF and TrojansDelay PUF
Page 3 and 4: PUF Concept Function returning a si
Page 5: PUF TaxonomyThis talkNon silicon PU
Page 8 and 9: Delay PUF Principle: Differential D
Page 12 and 13: Glitch PUF Exploits the glitches of
Page 14 and 15: Table of Contents PUF overview Dela
Page 16 and 17: XOR arbiter PUF Proposed by Suh et
Page 18 and 19: Feed-Forward PUF Proposed by Gassen
Page 20 and 21: ASYNC PUF RO-PUF with better stabil
Page 22 and 23: Table of Contents PUF overview Dela
Page 24 and 25: PUF reliability Results from the UN
Page 26 and 27: Reliable Key generation Fuzzy extra
Page 28 and 29: ML attack on delay PUFs Modeling At
Page 30 and 31: Countermeasures Brute Force Attack

GDR SoC SiP

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