GDR SoC SiP

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Glitch PUF Exploits the glitches of a non-linear Boolean function Main drawback• Glitches hard to extract (lot of buffers + DFF)Daisuke Suzuki and Koichi Shimizu. 2010. The glitch PUF: a new delay-PUF architecture exploiting glitch shapes. InProceedings of the CHES'10. Springer-Verlag, Berlin, Heidelberg, 366-382page 12Télécom ParisTechGDR SoC SiP
Brief comparisonDelay PUFMemory PUFGlitch PUFPros• Unique• Many challenges• Implementable inany technology• Unique• Implementable inDFF or nonintialized memory• UniqueCons• Sensitive tomodeling attack• Needs effort at P/R• Not steady• Few challenges• Not steady• Not yet mature• Need complexhardware to extractglitches• Not steadypage 13Télécom ParisTechGDR SoC SiP
Page 1 and 2: GDR SoC SiPPUF and TrojansDelay PUF
Page 3 and 4: PUF Concept Function returning a si
Page 5: PUF TaxonomyThis talkNon silicon PU
Page 8 and 9: Delay PUF Principle: Differential D
Page 10 and 11: Memory PUFMore details given in the
Page 14 and 15: Table of Contents PUF overview Dela
Page 16 and 17: XOR arbiter PUF Proposed by Suh et
Page 18 and 19: Feed-Forward PUF Proposed by Gassen
Page 20 and 21: ASYNC PUF RO-PUF with better stabil
Page 22 and 23: Table of Contents PUF overview Dela
Page 24 and 25: PUF reliability Results from the UN
Page 26 and 27: Reliable Key generation Fuzzy extra
Page 28 and 29: ML attack on delay PUFs Modeling At
Page 30 and 31: Countermeasures Brute Force Attack

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