8 BIT 4-CHANNEL D/A CONVERTER MB86022

DS04–13201–3aE
DATA SHEET
LINEAR IC CMOS
8 BIT 4-CHANNEL D/A CONVERTER
MB86022
CMOS 8-BIT 4-CHANNEL D/A CONVERTER
The Fujitsu MB86022 is a 8-bit 4-channel Digital to Analog Converter which is
fabricated with Fujitsu CMOS Technology. The data latch and output buffer circuitry
are provided on each channel which can operate independently selected by 2bit
data.
PLASTIC PACKAGE
DIP-24P-M03
• Resolution
• Conversion Rate
• Digital Input Voltage
: 8-Bits (4-channels)
: 200k sps
: TTL Level
PLASTIC PACKAGE
FPT-24P-M02
• Power Supply Voltage : +5V
• Low Power Dissipation : 14mW typ. at +5V
• Each channel operates independently
• On-chip Data Initialization & Power Down Function
• Reference voltage mode selection: On-chip or External generation
• Easy to take interface with micro processor (Parallel Data Input)
D0
D1
D2
D3
D4
D5
D6
D7
C0
C1
___
WR
___
CE
PIN ASSIGNMENT
1
2
3
4
5
6
7
8
9
10
11
12
(TOP VIEW)
24
23
22
21
20
19
18
17
16
15
14
13
______
RESET
___
PD
V DD
VR2
VR1
AO0
AO1
AO2
AO3
N.C.
AG
DG
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric fields.
However, it is advised that normal precautions be taken to
avoid application of any voltage higher than maximum rated
voltages to this high impedance circuit.
Quick Pro TM is a trademark of FUJITSU LIMITED
Copyright © 1995 by FUJITSU LIMITED
1

MB86022
ABSOLUTE MAXIMUM RATINGS (See NOTE)
Parameter
Rating
Symbol Pin Name Unit
Min Typ Max
Power supply voltage
V DD
V DD
GND–0.3
–
7
V
Digital input voltage
V DI
All digital input pins
GND–0.3
–
V DD +0.3
V
Analog input voltage V 1 , V 2
VR1,VR2
GND–0.3
–
V DD +0.3
V
Analog output voltage
V AO
AO0,AO1,AO2,AO3
GND–0.3
–
V DD +0.3
V
Analog output current I AO AO0,AO1,AO2,AO3 –10 – 10
mA
Storage temperature Tstg –40 – 125 °C
NOTE:
Permanent device damage may occur if the above Absolute Maximum Ratings are
exceeded. Functional operation should be restricted to the conditions as detailed in the
operational sections of this data sheet. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
2

MB86022
BLOCK DIAGRAM
D0 to D7
8
8-bit
Data
Latch
8-bit
DAC
–
+
AO3
Buffer Amp.
8-bit
Data
Latch
8-bit
DAC
–
+
AO2
Buffer Amp.
C0,C1
___
WR
___
CE
2
Channel
Select
&
Control
Logic
8-bit
Data
Latch
8-bit
DAC
–
+
Buffer Amp.
AO1
8-bit
Data
Latch
8-bit
DAC
–
+
AO0
______
RESET
___
PD
Buffer Amp.
VR1
VR2
V REF
Circuit
V DD
DG
AG
3

MB86022
PIN DESCRIPTION
System Pin Number Symbol Descriptions
Power
Supply
22 V DD Power Supply Voltage 5V
13 DG
14 AG
___
23 PD
GND for Digital System
GND for Analog System
Power down control signal pin. The circuit is set power down when this pin goes to “L”.
This pin is pulled up by high resistance. TTL interface.
24
______
RESET
Reset input signal pin. The data at all channels is initialized when this pin goes to “L”.
At this time, the D/A output is set at D(A)=128.
This pin is pulled up by high resistance. TTL interface.
12
11
___
CE
___
WR
Chip enable signal pin. The data can be written when this pin goes to “L”. This pin is
pulled up by high resistance. TTL interface.
Data write pin. The data from D0 to D7 is written when the rising edge (L H) of this pin.
TTL interface.
9
C0
Channel selection signal pin. Channels are selected by following table. TTL
interface.
Digital
Input
10
C1
C1 C0 Channel
L L 0
L H 1
H L 2
H H 3
1
2
3
D0
D1
D2
Data input signal pin. The digital data is read by the channel which is selected by C0 and
C1 pins when the rising edge of WR (L H), and analog output is shown correspond to
that digital code. D0 is LSB and D7 is MSB. Code is set at 10000000 when reset. TTL
interface.
4
D3
5
D4
6
D5
7
D6
8
D7
Analog
Input
20 VR 1
Reference voltage (H level) input pin. V DD is given by internal reference voltage circuitry
to this pin when internal reference voltage mode. In this case, the capacitor between
this pin and AG pin is required to limit noise generation. In case of external reference
voltage mode, the reference voltage should be given from this pin.
21 VR 2
Middle point of reference voltage input pin.
___ 1
Reference voltage (H level) input pin. 2 V DD is given by internal reference voltage circuitry
to this pin when internal reference voltage mode. In this case, the capacitor between
this pin and AG pin is required to limit noise generation. In case of external reference
voltage mode, the reference voltage should be given from this pin.
4

MB86022
(Continued)
System Pin Number Symbol Descriptions
16 AO3 Analog output pin of channel 3. This pin is set to high–impedance state at Power Down.
Analog 17 AO2 Analog output pin of channel 2. This pin is set to high–impedance state at Power Down.
Output
18 AO1 Analog output pin of channel 1. This pin is set to high–impedance state at Power Down.
19 AO0 Analog output pin of channel 0. This pin is set to high–impedance state at Power Down.
– 15 N.C. No connection pin
5

MB86022
RECOMMENDED OPERATING CONDITIONS
Parameter Symbol Pin Name
Value
Min Typ Max
Unit
Power supply voltage
V DD
V DD
4.75 5.0 5.25
V
Digital input voltage
V DI
All digital input pins
0 –
V DD
V
Analog input voltage
V 1
V 2
VR1
VR2
1.2 3.75 3.8
______ V 1 +1.2
2.5 ______ V 1 +3.8
2
2
V
V
Analog output load
resistance
Analog output load
capacitance
R AL
C AL
AO0, AO1, AO2, AO3
20 – –
– – 50
kΩ
pF
Operating temperature
Ta
–20 – 70
°C
6

MB86022
ELECTRICAL CHARACTERISTICS
Parameter Symbol Pin Name
I DD1
Power supply current
V DD
I DD2
Conditions
___
PD=“H”
No
load ___
PD=“L”
(V DD =4.75V to 5.25V, Ta=–20°C to 70°C)
Value
Unit
Min Typ Max
– 2.8 5.5 mA
– – 0.5 mA
Digital
input
“L” Voltage
“H” Voltage
“L” Current
“H” Current
V IL
V IH
I IL
I IH
All digital input pins
___
D0 to D7, WR
V DI =GND
V DI =V DD
0 – 0.8
2.2 – V DD
–10 – 10
–10 – 10
V
V
µA
µA
Pull up current
___
WR “H” Width
___
WR “L” Width
Digital input “L” width
DATA Set up time 1
DATA Set up time 2
___
CE Set up time
DATA Hold time 1
DATA Hold time 2
___
CE Hold time
I PLU
t WHWR
t WLWR
t WLRP
t SD1
t SD2
t SCE
t HD1
t HD2
t HCE
___ ___ ______
PD, CE, RESET
___
WR
___
WR
______ ___
RESET, PD
___
D0 to D7, WR
___
C0, C1, WR
___ ___
CE, WR
___
D0 to D7, WR
___
C0, C1, WR
___ ___
CE, WR
V DI =GND
Ref. to timing chart
Ref. to timing chart
Ref. to timing chart
Ref. to timing chart
Ref. to timing chart
Ref. to timing chart
Ref. to timing chart
Ref. to timing chart
Ref. to timing chart
–100 –50 –25
200 – –
200 – –
500 – –
100 – –
100 – –
0 – –
50 – –
50 – –
0 – –
µA
ns
ns
ns
ns
ns
ns
ns
ns
ns
7

MB86022
(Continued)
(V DD =4.75V to 5.25V, Ta=–20°C to 70°C)
Value
Parameter Symbol Pin Name
Conditions
Min Typ Max
Unit
Rising time 1 t r1
___
WR Ref. to timing chart 0 – 50 ns
Falling time 1 t f1
___
WR Ref. to timing chart
0 – 50 ns
Rising time 2 t r2
D0 ___ to D7, ______ C0,
C1, CE, ___ RESET, Ref. to timing chart 0 – 50 ns
PD
Falling time 2 t f2
D0 ___ to D7, ______ C0,
C1, CE, ___ RESET, Ref. to timing chart
0 – 50 ns
PD
Resolution Res
– 8 – bits
Analog output
Min. voltage
Analog output
Max. voltage
Analog input
resistance
V AOL1
V AOL2
V AOH1
V AOH2
R I
AO0,
AO1,
AO2,
AO3
VR 1 ,
VR 2
Input
code
D(A)=
0
Input
code
D(A)=
255
No external VR input
VR1=open
(Typ.) –0.1
____ V DD (Typ.) +0.1 V
VR2=open
4
External VR input
VR1=V 1
(Typ.) –0.1 2xV 2 –V 1
VR2=V (Typ.) +0.1 V
2
No external VR input
VR1=open
(Typ.) –0.1 ____ 383 x VDD (Typ.) +0.1 V
VR2=open
512
External VR input
VR1=V 1
(Typ.) –0.1 V 1 –_____
V 1 –V 2 (Typ.) +0.1 V
VR2=V 2 128
30 50 200
kΩ
Linearity error LE AO0, No external VR input
–1.5 – 1.5
VR1=open
Differential
AO1,
D VR2=open
linearity error
LE
–1 – 1
AO2,
Full scale change
Setting time t S AO3
(Ref. to timing chart)
– – 5
LSB
LSB
µs
8

MB86022
FUNCTION DESCRIPTION
TRUTH TABLE
___ ______ ___ ___
PD RESET CE WR
C0, C1
D0 to D7
Function
0
x
x
x
–
–
Power down
1 0 x x
1 1 1 x
– – Initialization
– No data input No analog output change
1 1 0
Channel selectiion
Data input
Analog output change
Fig. 1 – DATA SET TIMING DIAGRAM
D0 to D7
C0, C1
___
CE
___
WR
Data is read.
Analog output is changed.
Data is not read.
Analog output is not changed.
9

MB86022
SETTING OF ANALOG OUTPUT VOLTAGE
Data
Analog Output Voltage
D(A)
D7
D6
D5
D4
D3
D2
D1
D0
VR1=Open
VR2=Open
(No external VR input)
VR1=V 1
VR2=Open
(External VR1 input)
VR1=V 1
VR2=V 2
(External VR input)
255
1
1
1
1
1
1
1
1
____ 383 x VDD
512
_________ 2xV 1 –V DD
x 127 +
____ V DD
256
2
______ V 1 –V 2
128 x 127 + V 2
254 1 1 1 1 1 1 1 0
____ 382
512
x V DD
_________ 2xV 1 –V DD
x 126 + ____ V DD
256
2
______ V 1 –V 2
128 x 126 + V 2
253 1 1 1 1 1 1 0 1
⋅
⋅
____ 381
512
x V DD
____ V DD
512 x (D(A)–128) + ____ V DD
2
_________ 2xV 1 –V DD
x 125 + ____ V DD
256
2
_________ 2xV 1 –V DD
x (D(A) –128)
256
____ V
+ DD
2
______ V 1 –V 2
128 x 125 + V 2
______ V 1 –V 2
128 x (D(A)–128) + V 2
129 1 0 0 0 0 0 0 1
____ 257
512
x V DD
_________ 2xV 1 –V DD + ____ V DD
256 2
______ V 1 –V 2
128
128 1 0 0 0 0 0 0 0
127 0 1 1 1 1 1 1 1
____ 255
512
____ V DD
2
x V DD
________ 2xV 1 –V DD
256
____ V DD
2
x (–1) + ____ V DD
2
V 2
______ V 1 –V 2
x (–1)
128
+ V 2
+ V 2
126 0 1 1 1 1 1 1 0
____ 254
512
x V DD
________ 2xV 1 –V DD
x (–2) + ____ V DD
256
2
______ V 1 –V 2
x (–2) + V
128
2
⋅
⋅
⋅
⋅
⋅
2 0 0 0 0 0 0 1 0
____ 130
512
x V DD
2xV ________ 1 –V DD
256
x (–126) + ____ V DD
2
______ V 1 –V 2
x (–126) + V 2
128
1 0 0 0 0 0 0 0 1
____ 129
512
x V DD
2xV ________ 1 –V DD
256
x (–127) + ____ V DD
2
______ V 1 –V 2
128
x (–127) + V 2
0 0 0 0 0 0 0 0 0
____ V DD
4
V DD –V 1
–(V 1 –V 2 ) + V 2
1LSB
____ V DD
512
2xV ________ 1 –V DD
256
______ V 1 –V 2
128
* Code is set at ”10000000” when reset mode.
10

MB86022
ANALOG OUTPUT VOLTAGE RANGE
Fig. 2 – ON-CHIP REFERENCE VOLTAGE MODE (NO EXTERNAL VR INPUT)
__
4
V DD
1LSB
____ V DD
512
3 x VDD
____
V AOH
____ 383 xVDD
512
____ V DD
2
D/A Output range
V AOL
V DD
4
AG
(VR1=V 1 , VR2=1/2xV DD )
Fig. 3 – EXTERNAL REFERENCE VOLTAGE MODE
V DD
1LSB
__________
2 x V 1 –V DD
256
(VR1) V 1
____ V DD
2
V AOH
__________
2 x V 1 –V DD
x 127 + ____ V DD
256
2
D/A Output range
V AOL (V DD –V 1 )
AG
(VR1=V 1 , VR2=V 2 )
Fig. 4 – EXTERNAL REFERENCE VOLTAGE MODE
V DD
1LSB
______ V 1 –V 2
128
(VR1) V 1
V AOH
____ 127 x (V1 –V 2 ) + V 2
128
(VR2) V 2
D/A Output range
V AOL – (V 1 –V 2 ) + V 2
AG
11

MB86022
TYPICAL APPLICATION CIRCUIT FOR EACH MODE
Fig. 5 – ON-CHIP REFERENCE VOLTAGE MODE
D0 to D7
C0
___ C1
___ WR
CE
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
N.C.
______
___ RESET
PD
+5V (V DD )
+
– 1µF
AO0 to 3
+
– 1µF
Fig. 6 – EXTERNAL REFERENCE VOLTAGE MODE
D0 to D7
C0
___ C1
___ WR
CE
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
N.C.
______
___ RESET
PD
+5V (V DD )
V 1
+
– 1µF
AO0 to 3
(VR1=V 1 , VR2=1/2xV DD )
Fig. 7 – EXTERNAL REFERENCE VOLTAGE MODE
D0 to D7
C0
___ C1
___ WR
CE
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
N.C.
______
___ RESET
PD
+5V (V DD )
V 2
V 1
AO0 to 3
(VR1=V 1 , VR2=V 2 )
12

MB86022
TIMING DIAGRAM
___
WR
V IH
V IL
t r1
t f1
t WHWR t WLWR
t SD1 t HD1
D0 to D7
V IH
V IL
t r2
t f2
C0, C1
V IH
V IL
t r2
t SD2
t HD2
t f2
___
CE
V IH
V IL
t f2
t SCE t HCE
t r2 ±1LSB
AO0 to AO3
t S
±1LSB
______ ___
RESET, PD
V IH
V IL
t WLRP
13

MB86022
PACKAGE DIMENSIONS
24-LEAD PLASTIC DUAL IN-LINE PACKAGE
(CASE No.: DIP-24P-M03)
15°MAX
INDEX-1
.260±.010
(6.60±0.25)
.300(7.62)
TYP
INDEX-2
1.170 +.008
–.012 (29.72 +0.20
–0.30
)
.010±.002
(0.25±0.05)
.050(1.27)
MAX
.034 +.020
–0
+0.50
(0.86
–0
)
.172(4.36)MAX
.118(3.00)MIN
.100(2.54)
TYP
.050 +.020
–0
+0.50
(1.27
–0
)
.018±.003
(0.46±0.08)
.020(0.51)MIN
©1991 FUJITSU LIMITED D24017S-3C
Dimensions in
inches (millimeters)
14

MB86022
24-LEAD PLASTIC FLAT PACKAGE
(CASE No.: FPT-24P-M02)
+.010 +0.25
.600 (15.24 )
–.008 –0.20
.110(2.80) MAX
(MOUNTING HEIGHT)
.002(0.05) MIN
(STAND OFF HEIGHT)
INDEX
.402±.016
(10.20±0.40)
.299±.012
(7.60±0.30)
.362±.012
(9.20±0.30)
.050(1.27)
TYP
.018±.004
(0.45±0.10)
∅.005(0.13) M
.020±.008
(0.50±0.20)
.006 +.002 +0.05
–.001
(0.15 –0.02
)
Details of “A” part
“A”
.008(0.20)
©1991 FUJITSU LIMITED F24008S-4C
.004(0.10)
.550(13.97) REF
.024(0.60)
.007(0.18)
MAX
.027(0.68)
MAX
Dimensions in
inches (millimeters)
All Rights Reserved.
Circuit diagrams utilizing Fujitsu products are included as a means of illustrating typical
semiconductor applications. Complete Information sufficient for construction purposes
is not necessarily given.
The Information contained in this document has been carefully checked and is believed
to be reliable. However, Fujitsu assumes no responsibility for inaccuracies.
The Information contained in this document does not convey any license under the
copyrights, patent rights or trademarks claimed and owned by Fujitsu.
Fujitsu reserves the right to change products or specifications without notice.
No part of this publication may be copied or reproduced in any form or by any means, or
transferred to any third party without prior written consent of Fujitsu.
15

MB86022
For further information please contact:
Japan
FUJITSU LIMITED
Electronic Devices
International Operations Department
KAWASAKI PLANT, 1015 Kamikodanaka,
Nakahara–ku, Kawasaki–shi,
Kanagawa 211, Japan
Tel: (044) 754–3753
FAX: (044) 754–3332
North and South America
FUJITSU MICROELECTRONICS, INC.
Semiconductor Division
3545 North First Street
San Jose, CA 95134–1804, USA
Tel: (408) 922–9000
FAX: (408) 432–9044/9045
Europe
FUJITSU MIKROELEKTRONIK GmbH
Am Siebenstein 6–10
63303 Dreieich–Buchschlag,
Germany
Tel: (06103) 690–0
FAX: (06103) 690–122
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE LIMITED
No. 51 Bras Basah Road,
Plaza By The Park,
#06–04 to #06–07
Singapore 0718
Tel: 336–1600
FAX: 336–1609
I9502
© FUJITSU LIMITED Printed in Japan
16