LÜ-LCD-Dispalys_14

TFT TRANSMISSIVE LCD MODULES
YTS 280DLAC-03-200N
2.8’’, 240 X 320 DOTS, 1/320 DUTY
INTERFACE TIMING CHARACTERISTICS V SSA = 0V, IOCC=1.65V to 2.9V, VCI=2.3V to 2.9V, Ta=-30°C to 70°C
Parallel Interface Characteristics (8080 Series MPU)
Note (1): The input signal rise time and fall time (t r, t f) is specified at 15 ns or less.
Logic high and low levels are specified as 30% and 70% of IOV CC for input signals.
Parallel Interface Characteristics (6800 Series MPU)
Note (2): The input signal rise time and fall time (t r, t f) is specified at 15 ns or less.
Logic high and low levels are specified as 30% and 70% of IOV CC for input signals.
PARAMETER SIGNAL SYMBOL TEST CONDITIONS MIN. MAX. UNIT
Address Hold Time
t AHT
10 ns
DNC_SCL Write/Read
Address Setup Time t AST 10 ns
Chip Select „H“
Pulse Width
t CHW 0 ns
Chip Select Setup
Time (Write)
t CS 35 ns
Chip Select Setup Time NCS t RCSFM 355 ns
Chip Select Wait
Time (Write/Read)
t CSF 10 ns
Chip Select Hold Time t CSH 10 ns
Write Cycle
t WC 100 ns
Control Pulse „H“ NWR_
Duration
t WRH 35 ns
RNW
Control Pulse „L“
Duration
t WRL 35 ns
Read Cycle
t RCFM
450 ns
Control Pulse „H“
NRD_E
When read from
Duration
t RDHFM 90 ns
GRAM
Control Pulse „L“
Duration
t RDLFM 355 ns
t Data Setup Time
15 ns
DST
Data Hold Time t
D 17 to D DHT for max. C
0
L=30 pF 10 ns
Read Access Time t RATFM for min. C L=8 pF 340 ns
Output Disable Time t ODH 20 80 ns
PARAMETER SIGNAL SYMBOL TEST CONDITIONS MIN. MAX. UNIT
Address Hold Time
t AHT
10 ns
DNC_SCL Write/Read
Address Setup Time t AST 10 ns
Chip Select „H“
Pulse Width
t CHW 0 ns
Chip Select Setup
Time (Write)
t CS 35 ns
Chip Select Setup Time NCS t RCSFM 355 ns
Chip Select Wait
Time (Write/Read)
t CSF 10 ns
Chip Select Hold Time t CSH 10 ns
Write Cycle
t WC 100 ns
Control Pulse „H“ NWR_
Duration
t WRH 35 ns
RNW
Control Pulse „L“
Duration
t WRL 35 ns
Read Cycle
t RCFM
450 ns
Control Pulse „H“
NRD_E
When read from
Duration
t RDHFM 90 ns
GRAM
Control Pulse „L“
Duration
t RDLFM 355 ns
t Data Setup Time
10 ns
DST
Data Hold Time t DHT 10 ns
Read Access Time (ID) D 17 to D
for max. C
0 t L=30 pF
RAT
for min. C L=8 pF
100
Read Access Time (FM) t RATFM 340 ns
Output Disable Time t ODH 20 80 ns
The Serial Interface Characteristics PARAMETER SIGNAL SYMBOL TEST CONDITIONS MIN. MAX. UNIT
Senal Clock Cycle (Write)
t SCYCW 100 ns
DNC_SCL „H“
Pulse Width (Write) DNC_SCL t SHW 35 ns
DNC_SCL „L“
Pulse Width (Write)
t SLW 35 ns
Data Setup Time (Write)
t SDS 30 ns
SDI
Data Hold Time (Write) t SDH 30 ns
Senal Clock Cycle (Read)
t SCYCR 150 ns
DNC_SCL „H“
Pulse Width (Read) DNC_SCL t SHR 60 ns
DNC_SCL „L“
Pulse Width (Read)
t SLR 60 ns
Access Time t ACC SD0 for max. C L=30pF, 45 100 ns
Output Disable Time t OH for min. C L=8 pF 15 100 ns
DNC_SCL to Chip Select DNC_SCL,
NCS
t SCC 15 ns
NCS „H“ Pulse Width
t CHW 45 ns
Chip Select Setup Time NCS t CSS 60 ns
Note (2): The input signal rise time and fall time (t r, t f) is specified at 15 ns or less.
Logic high and low levels are specified as 30% and 70% of IOV CC for input signals.
Chip Select Hold Time t CSH 65 ns
digital electronic gmbh Tel. +49 (0) 8221/708-0 Fax. +49 (0) 8221/708-80
All specifications subject to change without notice.
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