High performance HBM Known Good Stack Testing

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PDN Performance Results • Two approaches were used to evaluate PDN <strong>performance</strong> – Physical design data was extracted into an S-Parameter files using Cadence Sigrity SI tool – Actual measurements were done with a dual port VNA at the DUTlet on the full probe card – Results were simulated in the frequency domain using Agilent ADS simulator • To address the concern about power sharing due to imbalance between the ATE power planes a 1 mOhm resistance was simulated to evaluate this impact Marc Loranger John Oonk 14
PDN simulations vs. Measurements Power plane 1– VNA Measurement Power plane 2 – VNA Measurement Power plane 3 – VNA Measurement Power plane 1 – Extracted Simulation Power plane 2 – Extracted Simulation Power plane 3 – Extracted Simulation • Difference between extraction and VNA measurements is related to VNA measurements were done on decoupling capacitors as probe points • Performance in the 10MHz to 100Mhz range correlates reasonably well Marc Loranger John Oonk 15
Page 1 and 2: High performance HBM Known Good Sta
Page 3 and 4: High Bandwidth Memory (HBM) • Mar
Page 5 and 6: High Bandwidth Memory (HBM) • Sta
Page 7 and 8: HBM Stack Probing • Bottom of SoC
Page 9 and 10: UltraFLEX KGS Solution • Test cel
Page 11 and 12: Power Distribution Challenges • V
Page 13: PDN DUTlet Power Stack-up • The s
Page 17 and 18: PDN voltage drop across DUT ATE pow
Page 19 and 20: Known Good Stack At Speed Test 1066

High performance HBM Known Good Stack Testing

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