Pericom Solutions for PCI Express (PCIe) - Hy-Line
Pericom Solutions for PCI Express (PCIe) - Hy-Line
Pericom Solutions for PCI Express (PCIe) - Hy-Line
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Packet24 Family Key Features<br />
� 4 KEY DESIGN GOALS:<br />
1. Lowest Latency in the market:<br />
� Design goal – 150nS typical, 200nS across temp<br />
2. Lowest Power in the market:<br />
� No heat sinks required in 55degC still air<br />
3. Most Wanted feature set in the market:<br />
� Fully compliant to latest <strong>PCI</strong>SIG <strong>PCI</strong>e spec 1.1<br />
� Fully compliant to latest <strong>PCI</strong>SIG <strong>PCI</strong> spec 1.2<br />
� Read and Write to configuration registers via SM bus<br />
� Programmable PHY parameters by port via I2C bus<br />
� Programmable 128 or 256B payload<br />
� Programmable cut through or store/<strong>for</strong>ward<br />
� Isochronous traffic support<br />
4. Most Cost Effective in the market:<br />
� Wide ball spacing = more efficient PCB routing = less system cost<br />
� Lower Pd = less heat budget = less system cost<br />
� Efficient die design = less unit cost<br />
29 Copyright <strong>Pericom</strong> Semiconductor 2006<br />
PI7C9X20432<br />
4Port/32Lane<br />
Packet Switch<br />
PI7C9X20312<br />
Switch<br />
PI7C9X20312<br />
3Port/12Lane<br />
Packet Switch<br />
PI7C9X20324<br />
Switch<br />
PI7C9X20324<br />
3Port/24Lane<br />
Packet Switch<br />
PI7C9X20416<br />
4Port/16Lane<br />
Packet Switch<br />
PI7C9X20424<br />
Switch<br />
PI7C9X20424<br />
4Port/24Lane<br />
Packet Switch
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