TVS Diode Arrays

5 

TVS Diode Arrays 

Product Number Description Packaging Page 

TVS Protection with Filter and Termination 

SPUSB1AJT Upstream USB Port Terminator with ESD 

Suppression & EMI Filtering R1 = 12 ohms Surface Mount (SC70-6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217-219 

SPUSB1BJT Upstream USB Port Terminator With ESD 


SPUSB1CJT Upstream USB Port Terminator With ESD 


Avalanche Diode Arrays 

SP0502BAHT 2 Channel SMT Array Surface Mount (SOT23). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220-227 

SP0502BAJT 2 Channel SMT Array Surface Mount (SC70) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220-227 

SP0503BAHT 3 Channel SMT Array Surface Mount (SOT143). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220-227 

SP0504BAAT 4 Channel SMT Array Surface Mount (TSSOP8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220-227 

SP0504BAHT 4 Channel SMT Array Surface Mount (SOT23-5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220-227 

SP0504BAJT 4 Channel SMT Array Surface Mount (SC70-5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220-227 

SP0505BAHT 5 Channel SMT Array Surfact Mount (SOT23-6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220-227 

SP0505BAJT 5 Channel SMT Array Surface Mount (SC70-6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220-227 

SP0506BAAT 6 Channel SMT Array Surfact Mount (MSOP8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220-227 

High Voltage Rail Clamp SCR/Diode Arrays 

SP720AB (T) 14 Channel SCR/Diode Array Surface Mount (SOIC16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228-233 

SP720AP 14 Channel SCR/Diode Array Leaded (PDIP16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228-233 

SP721AB (T) 6 Channel SCR/Diode Array Surface Mount (SOIC8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234-239 

SP721AP 6 Channel SCR/Diode Array Leaded (PDIP8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234-239 

SP723AB (T) 6 Channel High Energy SCR/Diode Array Surface Mount (SOIC8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240-245 

SP723AP 6 Channel High Energy SCR/Diode Array Leaded (PDIP8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240-245 

SP724AHT 4 Channel SCR Diode Array Surface Mount (SOT23-6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246-251 

216 

www.littelfuse.com


Upstream USB Port Terminator with ESD Suppression & EMI Filtering 

SPUSB1 Series 

The Littelfuse SPUSB1 Series is a multifunctional USB port protection 

network designed to provide ESD protection, EMI/RFI filtering and line 

termination for a single USB 1.1 port. The SPUSB1 can replace a minimum 

of ten typically larger “discrete” devices resulting in inventory and 

placement cost savings. 

The SPUSB1 Series combines Transient Voltage Suppression (TVS) 

avalanche diodes, EMI/RFI filtering components (R1 and C1), and 

a1.5kΩ termination resistor (R2). The filtering components are included 

to satisfy recommendations in the USB 1.1 specification, and the 1.5kΩ 

resistor (R2) is included as a pull-up resistor to VBUS. 

The SPUSB1 Series can be used for termination and protection 

of“upstream” USB devices such as PDAs, digital cameras, scanners and 

hubs which are often at risk from transient voltage surges and 

electromagnetic interference from both internal and external sources. 

To support a wide range of circuit conditions, Littelfuse offers three 

resistance values for the series resistor (R1). The series resistance plus 

the USB driver output resistance must be close to the USB cable’s characteristic 

impedance of 45Ω (90Ω balanced) to minimize transmission 

line reflections. 

Circuit Diagram 

Ordering Information 

PART 

NUMBER 

SPUSB1AJT 

SPUSB1BJT 

SPUSB1CJT 

1 

2 

GND 

3 

R1 (Ohm) 

12 

22 

33 

C1 

C1 

SC70-6 

R1 

R1 

R2 (KOhm) 

1.5 

1.5 

1.5 

R2 

V BUS 

6 

5 

4 

C1 (pF) 

47 

47 

47 

DEVICE 

BRAND 

UFA 

UFB 

UFC 

Features 

www.littelfuse.com 

• One upstream USB port terminator, EMI filter and transient 

overvoltage protector in a single surface-mount package 

• Compact SC70 package saves board space and lowers 

manufacturing costs compared to discrete solutions 

• ESD protection to 30kV contact discharge per MIL-STD- 883D, 

method 3015 

• ESD protection to 15kV contact discharge per IEC 61000-4-2 

international standard 

Applications 

• Desktop/Laptop PCs 

• USB peripherals (printers, scanners, zip drives) 

• PDAs / wireless handsets 

• Digital cameras 

• MP3 Players 

• Cable Modems 

PKG 

TYPE 

SC70-6 

SC70-6 

SC70-6 

#/REEL 

3000 

3000 

3000 

217 

5 

TVS DIODE ARRAYS



SPUSB1 Series 

218 

Supply Voltage VBUS 

DC Power per Resistor 

Package Power 

Temperature Range: 

Operating 

Storage 

Absolute Maximum Ratings 

Parameter Rating Unit 

5.5 

100 

200 

-40 to +85 

-65 to +150 

Standard 

Specifications 

(at 25°C unless specified otherwise) 

Parameter MIN TYP MAX Unit 

Resistance R1 (SPUSB1AJT only) 

6% 12 14% Ω 

Resistance R1 (SPUSB1CJT only) 

26% 33 40% Ω 

Resistance R1 (SPUSB1BJT only) 

18% 22 26% Ω 

Resistance R2 

1.2% 1.5 18% kΩ 

Capacitance C1 @ 2.5 v DC, 1MHz 

38% 47 56% pF 

Diode Leakage at 3.3V 

1 100 nA 

Diode Reverse Bias Stand-off Voltage, 1= 10µA 

Signal Clamp Voltage: 

5.5 

V 

Positive Clamp, 10mA 

5.6 6.8 8.0 V 

Negative Clamp, 10mA 

(1) 

In-system ESD Withstand Voltage 

-1.2 -0.8 -0.4 V 

Human Body Model (MIL-STD-883D, method 3015 

±30 

kV 

IEC 81000-4-2, contact discharge method (I/O pins) 

±15 

kV 

IEC 81000-4-2, contact discharge method (V 

BUS 

pin) 

±25 

kV 

(1) 

Clamping Voltage During ESD Discharge 

Positive 

10 

V 

MIL-STD-883D (Method 3015), 8kV 

Note: 

Negative 

-5 

V 

(1) ESD applied to input/outputV DD pins with respect to GND, one at a time. 

Clamping Voltage is measured at the opposite side of the EMI filter to the ESD pin (ie: if ESD is applied to pin1 then clamping 

voltage is measured at pin 6). Unused pins are open. 

These parameters guaranteed by design. 

APPLICATIONS INFORMATION 

D+ 

USB 1.1 

CONTROLLER 

IC 

GND 

D- 

1 

D1 

2 

GND 

3 

C1 

C1 

R1 

R1 

R2 

D4 

D2 D3 

6 

5 

V BUS 

4 

3.3V 

D+ 

USB 1.1 

CONNECTOR 

Figure 1. Full-Speed Devices (12Mbits per second) 

For full speed operation the pull-up resistor R2 is connected to the D+ pin. 

D- 

D- 

USB 1.1 

CONTROLLER 

IC 

GND 

D+ 


1 

D1 

2 

GND 

3 

V 

mW 

mW 

° C 

C1 

C1 

R1 

R1 

R2 

D4 

D2 D3 

6 

5 

V BUS 

4 

3.3V 

D- 

USB 1.1 

CONNECTOR 

Figure 2. Low-Speed Devices (1.5Mbits per second) 

Low speed connection requires the pull-up resistor R2 to be connected to the Dpin. 

Please note the reversal of the D- and D+ pins on Figure 2 versus Figure 1. 

D+



SPUSB1 Series 

PACKAGING INFORMATION 

Lead Plating 

Mechanical Specifications 

Tin-Lead 

Lead Material Copper Alloy 

Lead Coplanarity 0.004 inches (0.102mm) 

Subsitute Material Silicon 

Body Material Molded Epoxy 

Flammability UL94-V-0 

c 

Outline Drawings 

6 

1 2 3 

B 

B 

D 

5 

B 

4 

A1 

E HE 

A2 A 

L 

T 

P 

SPUSB1AJT - SC70-6 

SPUSB1BJT - SC70-6 

SPUSB1CJT - SC70-6 

Recommended Pad Layout 

S (REF) 

+ + + 

+ 

O (REF) 

+ + + 

R 

N (REF) 

M (REF) 


Package 

Pins 

JEDEC 

A 

A1 

A2 

B 

c 

D 

E 

e 

HE 

L 

M 

N 

O 

P 

R 

S 

T 

mm 

SC70-6 

6 

MO-203 Issue A 

inches 

min max min max 

0.80 1.10 0.031 0.043 

0.00 0.10 0.000 0.004 

0.70 1.00 0.028 0.039 

0.15 0.30 0.006 0.012 

0.08 0.25 0.003 0.010 

1.85 2.25 0.073 0.089 

1.15 1.35 0.045 0.053 

0.65 BSC 0.026 BSC 

2.00 2.40 

0.26 0.46 

PD@70°C 0.2W 

# / bag 1000 pcs 

# / tape & reel 3,000 pcs 

*See device brand for marking information. 

0.079 0.094 

0.010 0.018 

- 1.60 - 0.063 

- 1.30 - 0.052 

- 0.65 - 0.026 

- 0.70 - 0.058 

- 0.35 - 0.014 

- 0.90 - 0.035 

- 2.50 - 0.098 

219 

5 



Surface Mount TVS Avalanche Diode Array 

SP0502BA, SP0503BA, SP0504BA, SP0505BA, SP0506BA 

The surface mount family of arrays are designed to suppress ESD and 

other transient overvoltage events. These arrays are used to meet the 

International Electrotechnical Compatibility (IEC transient immunity standards 

IEC 61000-4-2 for Electrostatic Discharge Requirements). The 

series are used to help protect sensitive digital or analog input circuits 

on data, signal, or control lines with voltage levels up to 5VDC. 

The monolithic silicon arrays are comprised of specially designed 

structures for transient voltage suppression(TVS). The size and 

shape of these structures have be tailored for transient protection. 

The low capacitance and clamp voltage are ideal for high speed 

signal line protection. 


Part Number 

SP0502BAHT 

SP0503BAHT 

SP0504BAHT 

SP0505BAHT 

SP0504BAAT 

SP0506BAAT 

SP0502BAJT 

SP0504BAJT 

SP0505BAJT 

Pinout 

SP0502BAHT 

SP0502BAJT 

1 

1 

2 

SP0505BAHT 

SP0505BAJT 

2 

3 4 

220 

6 

3 

5 

CH 

2 

3 

4 

5 

4 

6 

2 

4 

5 

1 

Package Type 

SOT23 

SOT143 

SOT23-5 

SOT23-6 

TSSOP-8 

MSOP-8 

SC70-3 

SC70-5 

SC70-6 

SP0503BAHT 

4 

2 3 

SP0504BAAT 

8 7 6 5 

1 

2 

3 

4 

Quantity Per 

Reel 

3000 

3000 

3000 

3000 

4000 

4000 

3000 

3000 

3000 

SP0504BAHT 

SP0504BAJT 

1 

2 

3 4 

SP0506BAAT 

8 7 6 5 

1 

2 

3 

4 

5 

Features 


• An Array of 2, 3, 4, 5 or 6 TVS Avalanche Diodes in a ultra small 

SC70, SOT-23, SOT-143, MSOP or TSSOP packages 

• ESD Capability Standards 

IEC 61000-4-2, Direct Discharge . . . . . . . . . 20kV (Level 4) 

IEC 61000-4-2, Air Discharge . . . . . . . . . . . 30kV (Level 4) 

MIL STD 883 3015.7 . . . . . . . . . . . . . . . . . . . . . . . . . . 30kV 

• Input Protection for Applications Up to 5VDC 

• Fast Response Time . . . . . . . . . . . . . . . . . . . . . . . . . . . < 1ns 

• Low Input Capacitance . . . . . . . . . . . . . . . . . . . . 30pF Typical 

• Operating Temperature Range. . . . . . . . . . . . . -40°C to 85°C 

Applications 

• Mobile phone handsets 

• Personal Digital Assistants (PDA) 

• Portable handheld equipment (Laptop, Palmtop computers) 

• Computer port, keyboard (USB1.1) 

• Digital still cameras 

• Digital video cameras 

• MP3 players




Electrical Specifications TA = -25°C, Unless Otherwise Specified 

PARAMETER 

TEST CONDITIONS MIN 

TYPICAL MAX 

Reverse Standoff Voltage 

I = 10µA 

5.5 

- 

- 

Reverse Standoff Leakage Current 

Signal Clamp Voltage 

V = 5.0V 

1 

100 

Positive 

I = 10mA 

5.6 

6.8 

8 

Negative 

Clamp Voltage during ESD 

MIL-STD-883 Method 3015 (HBM) test 

I = 10mA 

-1.2 

-0.8 

-0.4 

8kV 

12 

8kV 

ESD Test Level (1) 

-8 

IEC-61000-2, Contact discharge 

20 

MIL-STD-883 Method 3015 (HBM) 

30 

Capacitance 

2.5V @ 1Mhz 

30 

Turn on/off Time 

Temperature Range 


Input Current (A) 



Typical Input VI Characteristics 

(Pulse-mode measurements, pulse width = 0.7 mS nominal) 

1.6 

1.4 

1.2 

1.0 

0.8 

0.6 

0.4 

0.2 

0.0 

-0.2 

-0.4 

-0.6 

-0.8 

-1.0 

-1.2 

-1.4 

-1.6 

-3 -2 -1 0 1 2 3 4 5 6 7 8 9 

Input Voltage (V) 

Package Information 

222 

Mechanical Specifications 

Lead Plating Tin-Lead 

Lead Material Copper Alloy 

Lead Coplanarity 0.004 inches (0.102mm) 

Subsitute Material Silicon 

Body Material Molded Epoxy 

Flammability UL94-V-0 

Notes: 

1. All dimensions are in millimeters. 

2. Dimensions include solder plating. 

3. Dimensions are exclusive of mold flash & metal burr. 

4. All specifications comply to JEDEC SPEC MO-203 ISSUE A. 

5. Blo is facing up for mold and facing down for trim/form, 

i.e. reverse trim/form. 

6. Package surface matte finish VDI 11-13. 


Diode Capacitance (pF) 

Typical Diode Capacitance 

vs. Reverse Voltage 

60 

40 

20 

0 

0 1 2 3 4 5 

Diode Reverse Voltage (V)




C 

c 

e 

B 

3 

502 

1 2 

D 

e 

e 

5 4 

1 2 3 

B 


e 

504 

D 

E 

A1 

HE 

A2 A 

A1 

L 

E HE 

A2 A 

L 

SP0502BAJT - SC70-3 



Package 

Pins 

JEDEC 

A 

A1 

A2 

B 

c 

D 

E 

e 

HE 

L 

Package 

Pins 

JEDEC 

A 

A1 

A2 

B 

c 

D 

E 

e 

HE 

L 

mm 

SC70-3 

3 


inches 


0.80 1.10 0.031 0.043 

0.00 0.10 0.00 0.004 

0.70 1.00 0.028 0.039 

0.15 0.30 0.006 0.012 

0.08 0.25 0.003 0.010 

1.85 2.25 0.073 0.089 

1.15 1.35 0.045 0.053 

0.66 BSC 0.026 BSC 

2.00 2.40 

0.26 0.46 

mm 

SC70-5 

5 


inches 


0.80 1.10 0.03 0.043 

0.00 0.10 0.00 0.004 

0.70 1.00 0.028 0.039 

0.15 0.30 0.006 0.012 

0.08 0.25 0.003 0.010 

1.85 2.25 0.073 0.089 

1.15 1.35 0.045 0.053 

0.65 BSC 0.026 BSC 

2.00 2.40 

0.26 0.46 

0.079 0.094 

0.010 0.018 

0.079 0.094 

0.010 0.018 

223 

5 





c 


C 

6 

1 2 3 

B 

e 

224 

D 

5 

e 

505 

e 

b 

3 

e1 

4 

502B 

1 2 

D 

A1 

E HE 

A2 A 

E1 

A1 

L1 

L 

E 

A 

T 

P 

P 



S (REF) 

+ + + 

SP0502BAHT - SOT23 


0 

+ 

O (REF) 

+ + + 

R 

N (REF) 

M 

N 

M (REF) 


Package 

Pins 

JEDEC 

A 

A1 

A2 

B 

c 

D 

E 

e 

HE 

L 

M 

N 

O 

P 

R 

S 

T 

Package 

Pins 

JEDEC 

A 

A1 

b 

c 

D 

E 

E1 

e 

e1 

L1 

M 

N 

O 

P 

mm 

SC70-6 

5 


inches 


0.80 1.10 0.031 0.043 

0.00 0.10 0.00 0.004 

0.70 1.00 0.028 0.039 

0.15 0.30 0.006 0.012 

0.08 0.25 0.003 0.010 

1.85 2.25 0.073 0.089 

1.15 1.35 0.045 0.053 

0.65 BSC 0.026 BSC 

2.00 2.40 

0.26 0.46 

- 

- 

- 

- 

- 

- 

- 

1.60 

1.30 

0.65 

0.70 

0.35 

0.90 

2.50 

0.079 0.094 

0.010 0.018 

- 0.063 

- 0.052 

- 0.026 

- 0.058 

- 0.014 

- 0.035 

- 0.098 

SOT23 

3 

TO-236 

mm inches 


0.89 1.12 0.035 0.044 

0.01 0.1 0.0004 0.004 

0.3 0.5 0.012 0.020 

0.08 0.2 0.003 0.008 

2.8 3.04 0.110 0.120 

2.1 2.64 0.083 0.104 

1.2 1.4 0.047 0.055 

0.95 BSC 0.95 BSC 

1.90 BSC 1.90 BSC 

0.54 REF 0.54 REF 

2.29 .090 

0.95 .0375 

0.78 .030TYP 

0.78 .030TYP




e1 

c 


c 

4 

e 

503B 

1 2 

D 

e1 

e 

5 4 

504B 

1 2 3 

D 

3 

B 

A1 

E1 

b2 b A1 

L1 

L 

E1 E 

L1 

A 

A 

E 

3.40 (.134") 

3.60 (.140") 

SP0504BAHT - SOT23-5 

P 

SP0503BAHT - SOT143 


0.80 (.032") 

1.00 (.040") 

2.20 

(.087") 

REF 


O 

1.90 

(.075") 

1.70 

(.067") 

BSC 

1.00 (.040") 

1.20 (.048") 

N 

0.80 (.032") 

1.00 (.040") 

1.40 (.055") 

MAX 

M 


Package 

Pins 

JEDEC 

A 

A1 

b 

b2 

c 

D 

E 

E1 

e 

e1 

L 

L1 

Package 

Pins 

JEDEC 

A 

A1 

b 

c 

D 

E 

E1 

e 

e1 

L1 

M 

N 

O 

P 

SOT143 

4 

TO-253 

mm inches 


0.08 1.22 0.031 0.048 

0.05 0.15 0.002 0.006 

0.30 0.50 0.012 0.019 

0.76 0.89 0.030 0.035 

0.08 0.20 0.003 0.008 

2.80 3.04 0.110 0.119 

2.10 2.64 0.082 0.103 

1.20 1.40 0.047 0.055 

1.92 BSC 0.076 BSC 

0.20 BSC 0.008 BSC 

0.4 0.6 0.016 0.024 

0.550 REF 0.022 REF 

SOT23-5 

5 

MO-178 

mm inches 


- 1.45 - 0.057 

0 0.15 0 0.006 

0.3 0.5 0.012 0.020 

0.08 0.22 0.003 0.009 

2.75 3.05 0.108 0.120 

2.6 3.0 0.102 0.118 

1.45 1.75 0.057 0.069 

0.95 BSC 0.95 BSC 

1.90 BSC 1.90 BSC 

0.60 REF 0.60 REF 

2.59 .102 

0.95 .038 

0.69 .027TYP 

0.99 .039TYP 

225 

5 






c 

E 

A 

L2 

6 

226 

e1 

e 

5 

505B 

1 2 3 

A1 

b 

D 

D 

4 

A1 

LF 

504 BA 

B 

E1 E 

L1 

A 

C 

L1 

E1 

SP0505BAHT - SOT23-6 

P 


O 

N 

M 


Package 

Pins 

JEDEC 

A 

A1 

b 

c 

D 

E 

E1 

e 

e1 

L1 

M 

N 

O 

P 

SOT23-6 

6 

MO-178 

mm inches 


- 1.45 - 0.057 

0 0.15 0 0.006 

0.3 0.5 0.012 0.020 

0.08 0.22 0.003 0.009 

2.75 3.05 0.108 0.120 

2.6 3.0 0.102 0.118 

1.45 1.75 0.057 0.069 

0.95 BSC 0.95 BSC 

1.90 BSC 1.90 BSC 

0.60 REF 0.60 REF 

PD@70°C .225W 

SP0504BAAT - TSSOP-8 Package TSSOP-8 

D 

E 

E1 

A 

A1 

B 

C 

L1 

L2 

2.59 .102 

0.95 0.038 

0.69 .027TYP 

0.99 .039TYP 

mm inches 


2.90 3.10 .144 .122 

6.40 REF .252 REF 

4.29 4.50 .17 .18 

1.194 REF .047 REF 

0.051 0.152 .002 0.006 

- 0.30 - .12TYP 

- 0.66 - .26TYP 

0.51 0.76 .020 .030 

0.102 0.203 .004 .008




E 


A 

A1 

L1 

D 

LF 

506 B 

B 

E1 

C 

L2 

SP0506BAAT - MSOP-8 


F 

G 

I 

H 

F1 


Package MSOP-8 

mm inches 


D 2.90 3.10 .144 .122 

E 4.78 4.98 .188 .196 

E1 2.90 3.10 .114 .122 

A 0.87 1.17 .034 .046 

A1 0.05 0.25 .002 0.10 

B 

- 0.30TYP - .12TYP 

C 

- 0.65TYP - .25TYP 

L1 0.52 0.54 .017 .025 

L2 

- 0.18TYP - .007TYP 

F 

- 5.28 - .208 

F1 

- 4.24 - .167 

G 

- 0.65 - .0256 

H 

- 0.38 - .015 

I 

- 1.04 

- .041 

227 

5 



Electronic Protection Array for ESD and Overvoltage Protection 

SP720 

The SP720 is an array of SCR/Diode bipolar structures for ESD and 

over-voltage protection to sensitive input circuits. The SP720 has 2 

protection SCR/Diode device structures per input. A total of 14 available 

inputs can be used to protect up to 14 external signal or bus lines. 

Over-voltage protection is from the IN (pins 1-7 and 9-15) to V+ or V-. 

The SCR structures are designed for fast triggering at a threshold of one 

+VBE diode threshold above V+ (Pin 16) or a -VBE diode threshold 

below V- (Pin 8). From an IN input, a clamp to V+ is activated if a transient 

pulse causes the input to be increased to a voltage level greater 

than one VBE above V+. A similar clamp to V- is activated if a negative 

pulse, one VBE less than V-, is applied to an IN input. Standard ESD 

Human Body Model (HBM) Capability is: 

HBM STANDARD MODE R C ESD (V) 

IEC 61000-4-2 Air 330Ω 150pF >15kV 

Refer to Figure 1 and Table 1 for further detail. Refer to Application Note 

AN9304 and AN9612 for additional information. 


228 

Direct 330Ω 150pF >4kV 

Direct, Dual Pins 330Ω 150pF >8kV 

MIL-STD-3015.7 Direct, In-circuit 1.5kΩ 100pF >15kV 

TEMP. RANGE 

PART NO. ( o PKG. Min. 

C) PACKAGE NO. Order 

SP720AP -40 to 105 16 Ld PDIP E16.3 1500 

SP720AB -40 to 105 16 Ld SOIC M16.15 1970 

SP720ABT -40 to 105 16 Ld SOIC 

Tape and Reel 

M16.15 2500 

Pinout 

SP720 (PDIP, SOIC) 

IN 

IN 

IN 

IN 

IN 

IN 

IN 

V- 

1 

2 

3 

4 

5 

6 

7 

8 

TOP VIEW 

16 

15 

14 

13 

12 

11 

10 

9 

V+ 

IN 

IN 

IN 

IN 

IN 

IN 

IN 

Features 


• ESD Interface Capability for HBM Standards 

- MIL STD 3015.7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15kV 

- IEC 61000-4-2, Direct Discharge, 

Single Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4kV (Level 2) 

Two Inputs in Parallel . . . . . . . . . . . . . . . . . . . . . . . . 8kV (Level 4) 

- IEC 61000-4-2, Air Discharge. . . . . . . . . . . . . . . . . 15kV (Level 4) 

• High Peak Current Capability 

- IEC 61000-4-5 (8/20µs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±3A 

- Single Pulse, 100µs Pulse Width. . . . . . . . . . . . . . . . . . . . . . . ±2A 

- Single Pulse, 4µs Pulse Width. . . . . . . . . . . . . . . . . . . . . . . . . ±5A 

• Designed to Provide Over-Voltage Protection 

- Single-Ended Voltage Range to . . . . . . . . . . . . . . . . . . . . . . +30V 

- Differential Voltage Range to. . . . . . . . . . . . . . . . . . . . . . . . . ±15V 

• Fast Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2ns Risetime 

• Low Input Leakages . . . . . . . . . . . . . . . . . . . . . . . . . 1nA at 25 o C (Typ) 

• Low Input Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3pF (Typ) 

• An Array of 14 SCR/Diode Pairs 

• Operating Temperature Range . . . . . . . . . . . . . . . . . . . . -40 o C to 105 o C 

Applications 

• Microprocessor/Logic Input Protection 

• Data Bus Protection 

• Analog Device Input Protection 

• Voltage Clamp 

Functional Block Diagram 

V+ 16 

IN 

V- 

1 

8 

IN 

2 

3 - 7 

9 - 15 

IN



SP720 


Thermal Information 

Continuous Supply Voltage, (V+) - (V-). ........................+35V Thermal Resistance (Typical, Note 1). ....................θJA ( 

Forward Peak Current, IIN to VCC , IIN to GND 

(Refer to Figure 6) . .................................±2A, 100µs 

ESD Ratings and Capability (Figure 1, Table 1) 

Load Dump and Reverse Battery (Note 2) 

oC/W) PDIP Package . ............................................90 

SOIC Package . ..........................................130 

Maximum Storage Temperature Range . . . .. ..............-65oC to 150oC Maximum Junction Temperature (Plastic Package) . ....................150oC Maximum Lead Temperature (Soldering 10s) . .........................300oC (SOIC Lead Tips Only) 

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device 

at these or any other conditions above those indicated in the operational sections of this specification is not implied. 

NOTE: 

1. θJA is measured with the component mounted on an evaluation PC board in free air. 

Electrical Specifications T A = -40 o C to 105 o C; V IN = 0.5V CC , Unless Otherwise Specified 

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS 

Operating Voltage Range, 

VSUPPLY = [(V+) - (V-)] 

VSUPPLY - 2 to 30 - V 

Forward Voltage Drop: 

IN to V- 

IN to V+ 

ESD Capability 

V FWDL 

V FWDH 

ESD capability is dependent on the application and defined test 

standard. The evaluation results for various test standards and methods 

based on Figure 1 are shown in Table 1. 

For the “Modified” MIL-STD-3015.7 condition that is defined as an 

“in-circuit” method of ESD testing, the V+ and V- pins have a return path 

to ground and the SP720 ESD capability is typically greater than 15kV 

from 100pF through 1.5kΩ. By strict definition of MIL-STD-3015.7 using 

“pin-to-pin” device testing, the ESD voltage capability is greater than 6kV. 

The MIL-STD-3015.7 results were determined from AT&T ESD Test 

Lab measurements. 

The HBM capability to the IEC 61000-4-2 standard is greater than 15kV 

for air discharge (Level 4) and greater than 4kV for direct discharge 

(Level 2). Dual pin capability (2 adjacent pins in parallel) is well in excess 

of 8kV (Level 4). 

For ESD testing of the SP720 to EIAJ IC121 Machine Model (MM) standard, 

the results are typically better than 1kV from 200pF with no series resistance. 

I IN = 1A (Peak Pulse) 

Input Leakage Current IIN -20 5 20 nA 

Quiescent Supply Current IQUIESCENT - 50 200 nA 

Equivalent SCR ON Threshold Note 3 - 1.1 - V 

Equivalent SCR ON Resistance VFWD/IFWD; Note 3 - 1 - Ω 

Input Capacitance CIN - 3 - 

pF 

Input Switching Speed 

NOTES: 

tON - 2 - 

ns 

2. In automotive and battery operated systems, the power supply lines should be externally protected for load dump and reverse battery. When the 

V+ and V- pins are connected to the same supply voltage source as the device or control line under protection, a current limiting resistor should 

be connected in series between the external supply and the SP720 supply pins to limit reverse battery current to within the rated maximum 

limits. Bypass capacitors of typically 0.01µF or larger from the V+ and V- pins to ground are recommended. 

3. Refer to the Figure 3 graph for definitions of equivalent “SCR ON Threshold” and “SCR ON Resistance.” These characteristics are given here 

for thumb-rule information to determine peak current and dissipation under EOS conditions. 


- 

- 

2 

2 

TABLE 1. ESD TEST CONDITIONS 

STANDARD TYPE/MODE R D CD ±VD MIL STD 3015.7 Modified HBM 1.5kΩ 100pF 15kV 

Standard HBM 1.5kΩ 100pF 6kV 

IEC 61000-4-2 HBM, Air Discharge 330Ω 150pF 15kV 

HBM, Direct Discharge 330Ω 150pF 4kV 

HBM, Direct Discharge, 

Two Parallel Input Pins 

330Ω 150pF 8kV 

EIAJ IC121 Machine Model 0kΩ 200pF 1kV 

H.V. 

SUPPLY 

°±V D 

CHARGE 

SWITCH 

R 1 

C D 

R D 

- 

- 

DISCHARGE 

SWITCH 

IEC 1000-4-2: R1 50 to 100MΩ 

MIL STD 3015.7: R1 1 to 10MΩ 

IN 

DUT 

V 

V 

FIGURE 1. ELECTROSTATIC DISCHARGE TEST 

229 

5 




SP720 

230 

FORWARD SCR CURRENT (mA) 

100 

80 

60 

40 

20 

T A = 25 o C 

SINGLE PULSE 

0 

600 800 1000 1200 

FORWARD SCR VOLTAGE DROP (mV) 

FIGURE 2. LOW CURRENT SCR FORWARD VOLTAGE DROP 

CURVE 

+V CC 

INPUT 

DRIVERS 

OR 

SIGNAL 

SOURCES 

SP720 

SP720 INPUT 

PROTECTION CIRCUIT 

(1 OF 14 ON CHIP) 

IN 1-7 

FORWARD SCR CURRENT (A) 

2.5 


2 

1.5 

1 

0.5 

0 

T A = 25 o C 

SINGLE PULSE 

EQUIV. SAT. ON 

THRESHOLD ~ 1.1V 

V FWD 

I FWD 

0 1 2 3 

FORWARD SCR VOLTAGE DROP (V) 

FIGURE 3. HIGH CURRENT SCR FORWARD VOLTAGE DROP 

CURVE 

FIGURE 4. TYPICAL APPLICATION OF THE SP720 AS AN INPUT CLAMP FOR OVER-VOLTAGE, GREATER THAN 1V BE ABOVE V+ OR 

LESS THAN -1V BE BELOW V- 

IN 9-15 

V- 

+V CC 

LINEAR OR 

DIGITAL IC 

INTERFACE 

V+ 

TO +V CC



SP720 

Peak Transient Current Capability of the SP720 

The peak transient current capability rises sharply as the width of the 

current pulse narrows. Destructive testing was done to fully evaluate the 

SP720’s ability to withstand a wide range of transient current pulses. The 

circuit used to generate current pulses is shown in Figure 5. 

The test circuit of Figure 5 is shown with a positive pulse input. For a 

negative pulse input, the (-) current pulse input goes to an SP720 ‘IN’ 

input pin and the (+) current pulse input goes to the SP720 V- pin. The 

V+ to V- supply of the SP720 must be allowed to float. (i.e., It is not tied 

to the ground reference of the current pulse generator.) Figure 6 shows 

the point of overstress as defined by increased leakage in excess of the 

data sheet published limits. 

The maximum peak input current capability is dependent on the V+ to Vvoltage 

supply level, improving as the supply voltage is reduced. Values 

of 0, 5, 15 and 30 voltages are shown. The safe operating range of the 

transient peak current should be limited to no more than 75% of the 

measured overstress level for any given pulse width as shown in Figure 6. 

When adjacent input pins are paralleled, the sustained peak current 

capability is increased to nearly twice that of a single pin. For comparison, 

tests were run using dual pin combinations 1+2, 3+4, 5+6, 7+9, 

10+11, 12+13 and 14+15. 

PEAK CURRENT (A) 

10 

9 

8 

7 

6 

5 

4 

3 

2 

1 

0 

0.001 0.01 0.1 1 

PULSE WIDTH TIME (ms) 


The overstress curve is shown in Figure 6 for a 15V supply condition. The 

dual pins are capable of 10A peak current for a 10µs pulse and 4A peak 

current for a 1ms pulse. The complete for single pulse peak current vs. 

pulse width time ranging up to 1 second are shown in Figure 6. 

+ 

VG - 

R 1 

VOLTAGE 

PROBE 

R1 ~ 10Ω TYPICAL 

VG ADJ. 10V/A TYPICAL 

C1 ~ 100µF 

(+) 

VARIABLE TIME DURATION 

CURRENT PULSE GENERATOR 

CURRENT 

SENSE 

1 IN V+ 16 

2 IN IN 15 

3 IN IN 14 

4 

5 

IN 

IN 

SP720 

IN 

IN 

13 

12 

6 IN IN 11 

7 IN IN 10 

8 V- IN 9 

FIGURE 5. TYPICAL SP720 PEAK CURRENT TEST CIRCUIT 

WITH A VARIABLE PULSE WIDTH INPUT 

CAUTION: SAFE OPERATING CONDITIONS LIMIT 

THE MAXIMUM PEAK CURRENT FOR A GIVEN 

PULSE WIDTH TO BE NO GREATER THAN 75% 

OF THE VALUES SHOWN ON EACH CURVE. 

SINGLE PIN STRESS CURVES 

DUAL PIN STRESS CURVE 

0V 

5V 

30V 

V+ TO V- SUPPLY 

10 

15V 

(-) 

15V 

C1 

100 1000 

FIGURE 6. SP720 TYPICAL SINGLE PULSE PEAK CURRENT CURVES SHOWING THE MEASURED POINT OF OVER-STRESS IN 

AMPERES vs PULSE TIME IN MILLISECONDS (T A = 25 o C) 

+ 

- 

231 

5 




SP720 

Dual-In-Line Plastic Packages (PDIP) 

INDEX 

AREA 

BASE 

PLANE 

SEATING 

PLANE 

D1 

B1 

NOTES: 

1. Controlling Dimensions: INCH. In case of conflict between English and 

Metric dimensions, the inch dimensions control. 

2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 

3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of 

Publication No. 95. 

4. Dimensions A, A1 and L are measured with the package seated in JE- 

DEC seating plane gauge GS-3. 

5. D, D1, and E1 dimensions do not include mold flash or protrusions. 

Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 

6. E and eA are measured with the leads constrained to be perpendicular 

to datum -C- . 

7. eB and eC are measured at the lead tips with the leads unconstrained. 

eC must be zero or greater. 

8. B1 maximum dimensions do not include dambar protrusions. Dambar 

protrusions shall not exceed 0.010 inch (0.25mm). 

9. N is the maximum number of terminal positions. 

10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, 

E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). 

232 

-A- 

N 

1 2 3 N/2 

B 

D 

e 

D1 

E1 

-B- 

-C- 

A1 

A2 

L 

A 

e C 

0.010 (0.25) M C A B S 

E 

C L 

e A 

C 

e B 


E16.3 (JEDEC MS-001 BB ISSUE D) 

16 LEAD DUAL-IN-LINE PLASTIC PACKAGE 

INCHES MILLIMETERS 

SYMBOL MIN MAX MIN MAX NOTES 

A - 0.210 - 5.33 4 

A1 0.015 - 0.39 - 4 

A2 0.115 0.195 2.93 4.95 - 

B 0.014 0.022 0.356 0.558 - 

B1 0.045 0.070 1.15 1.77 8, 10 

C 0.008 0.014 0.204 0.355 - 

D 0.735 0.775 18.66 19.68 5 

D1 0.005 - 0.13 - 5 

E 0.300 0.325 7.62 8.25 6 

E1 0.240 0.280 6.10 7.11 5 

e 0.100 BSC 2.54 BSC - 

eA 0.300 BSC 7.62 BSC 6 

eB - 0.430 - 10.92 7 

L 0.115 0.150 2.93 3.81 4 

N 16 

16 9



SP720 

Small Outline Plastic Packages (SOIC) M16.15 (JEDEC MS-012-AC ISSUE C) 

N 

INDEX 

AREA 

1 2 3 

-A- 

e 

D 

B 

E 

-C- 

-B- 

0.25(0.010) M C A M B S 

A 

H 

SEATING PLANE 

A1 

NOTES: 


Publication Number 95. 


3. Dimension “D” does not include mold flash, protrusions or gate burrs. 

Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 

inch) per side. 

4. Dimension “E” does not include interlead flash or protrusions. Interlead 

flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 

5. The chamfer on the body is optional. If it is not present, a visual index 

feature must be located within the crosshatched area. 

6. “L” is the length of terminal for soldering to a substrate. 

7. “N” is the number of terminal positions. 

8. Terminal numbers are shown for reference only. 

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above 

the seating plane, shall not exceed a maximum value of 0.61mm 

(0.024 inch). 

10. Controlling dimension: MILLIMETER. Converted inch dimensions are 

not necessarily exact. 

µ 

0.25(0.010) M B M 

0.10(0.004) 

L 

h x 45 o 

C 


16 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE 



A 0.0532 0.0688 1.35 1.75 - 

A1 0.0040 0.0098 0.10 0.25 - 

B 0.013 0.020 0.33 0.51 9 

C 0.0075 0.0098 0.19 0.25 - 

D 0.3859 0.3937 9.80 10.00 3 

E 0.1497 0.1574 3.80 4.00 4 

e 0.050 BSC 1.27 BSC - 

H 0.2284 0.2440 5.80 6.20 - 

h 0.0099 0.0196 0.25 0.50 5 

L 0.016 0.050 0.40 1.27 6 

N 16 16 7 

0 o 

8 o 

0 o 

8 o 

µ 

- 

233 

5 




SP721 


over-voltage protection to sensitive input circuits. The SP721 has 2 

protection SCR/Diode device structures per input. There are a total of 

6 available inputs that can be used to protect up to 6 external signal or 

bus lines. Over-voltage protection is from the IN (Pins 1 - 3 and Pins 

5 - 7) to V+ or V-. 


+V BE diode threshold above V+ (Pin 8) or a -V BE diode threshold below 

V- (Pin 4). From an IN input, a clamp to V+ is activated if a transient 

pulse causes the input to be increased to a voltage level greater than 

one V BE above V+. A similar clamp to V- is activated if a negative pulse, 

one V BE less than V-, is applied to an IN input. Standard ESD Human 

Body Model (HBM) Capability is: 

HBM 

STANDARD MODE R C ESD (V) 

IEC 61000-4-2 Air 330Ω 150pF >15kV 

Direct 330Ω 150pF >4kV 

Direct, Dual Pins 330Ω 150pF >8kV 

MIL-STD-3015.7 Direct, In-Circuit 1.5kΩ 100pF >15kV 

Refer to Figure 1 and Table 1 for further detail. Refer to Application 

Notes AN9304 and AN9612 for additional information. 


PART NO. 

TEMP. RANGE 

( oC) PACKAGE 

PKG. 

NO. 

Min. 

Order 




Tape and Reel 

M8.15 2500 

Pinout 

234 

IN 

IN 

IN 

V- 

SP721 (PDIP, SOIC) 

TOP VIEW 

1 

2 

3 

4 

8 

7 

6 

5 

V+ 

IN 

IN 

IN 

Features 


• ESD Interface Capability for HBM Standards 

- MIL STD 3015.7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15kV 

- IEC 61000-4-2, Direct Discharge, 

- Single Input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4kV (Level 2) 

- Two Inputs in Parallel . . . . . . . . . . . . . . . . . . . . . . . . . . 8kV (Level 4) 

- IEC 61000-4-2, Air Discharge . . . . . . . . . . . . . . . . . . 15kV (Level 4) 

• High Peak Current Capability 

- IEC 61000-4-5 (8/20µs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±3A 

- Single Pulse, 100µs Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . ±2A 

- Single Pulse, 4µs Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . . . ±5A 


- Single-Ended Voltage Range to . . . . . . . . . . . . . . . . . . . . . . . . +30V 

- Differential Voltage Range to. . . . . . . . . . . . . . . . . . . . . . . . . . . ±15V 

• Fast Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2ns Rise Time 

• Low Input Leakages . . . . . . . . . . . . . . . . . . . . . . . . 1nA at 25 o C Typical 

• Low Input Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3pF Typical 



Applications 






V+ 

IN 

V- 

8 

1 

4 

IN 2 

3, 5-7 

IN



SP721 



Continuous Supply Voltage, (V+) - (V-). ........................+35V Thermal Resistance (Typical, Note 1) θJA ( 

Forward Peak Current, IIN to VCC , IIN to GND 

(Refer to Figure 6). .................................±2A, 100µs 



oC/W) PDIP Package . ...........................................160 

SOIC Package . ..........................................170 

Maximum Storage Temperature Range . .................. .-65oC to 150oC Maximum Junction Temperature (Plastic Package) . . . .. ............. ..150oC Maximum Lead Temperature (Soldering 10s). ..........................300oC (SOIC Lead Tips Only) 



NOTE: 


Electrical Specifications T A = -40 o C to 105 o C, V IN = 0.5V CC , Unless Otherwise Specified 



VSUPPLY = [(V+) - (V-)] 

Forward Voltage Drop 

VSUPPLY - 2 to 30 - V 

IN to V- 

VFWDL IIN = 1A (Peak Pulse) - 

2 

- 

V 

IN to V+ 

VFWDH - 

2 

- 

V 

Input Leakage Current IIN -20 5 +20 nA 

Quiescent Supply Current IQUIESCENT - 50 200 nA 

Equivalent SCR ON Threshold Note 3 - 1.1 - V 

Equivalent SCR ON Resistance VFWD /IFWD ; Note 3 - 1 - Ω 

Input Capacitance CIN - 3 - pF 

Input Switching Speed 

NOTES: 

tON - 2 - ns 

2. In automotive and battery operated systems, the power supply lines should be externally protected for load dump and reverse battery. When the 

V+ and V- Pins are connected to the same supply voltage source as the device or control line under protection, a current limiting resistor should 

be connected in series between the external supply and the SP721 supply pins to limit reverse battery current to within the rated maximum 

limits. Bypass capacitors of typically 0.01µF or larger from the V+ and V- Pins to ground are recommended. 

3. Refer to the Figure 3 graph for definitions of equivalent “SCR ON Threshold” and “SCR ON Resistance”. These characteristics are given here 

for thumb-rule information to determine peak current and dissipation under EOS conditions. 


ESD capability is dependent on the application and defined test standard.The 

evaluation results for various test standards and methods based on Figure 1 

are shown in Table 1. 

For the “Modified” MIL-STD-3015.7 condition that is defined as an “in-circuit” 

method of ESD testing, the V+ and V- pins have a return path to ground and 

the SP721 ESD capability is typically greater than 15kV from 100pF through 

1.5kΩ. By strict definition of MIL-STD-3015.7 using “pin-to-pin” device testing, 

the ESD voltage capability is greater than 6kV. The MIL-STD-3015.7 results 

were determined from AT&T ESD Test Lab measurements. 

The HBM capability to the IEC 61000-4-2 standard is greater than 15kV 

for air discharge (Level 4) and greater than 4kV for direct discharge 

(Level 2). Dual pin capability (2 adjacent pins in parallel) is well in excess 

of 8kV (Level 4). 

For ESD testing of the SP721 to EIAJ IC121 Machine Model (MM) standard, 

the results are typically better than 1kV from 200pF with no series resistance. 



STANDARD TYPE/MODE R D C D ±V D 

MIL-STD-3015.7 Modified HBM 1.5kΩ 100pF 15kV 




HBM, Direct Discharge, 

Two Parallel Input Pins 

330Ω 150pF 8kV 


H.V. 

SUPPLY 

±V D 

CHARGE 

SWITCH 

R 1 

C D 

R D 

DISCHARGE 

SWITCH 

IEC 1000-4-2: R1 50 to 100MΩ 

MIL-STD-3015.7: R11 to 10MΩ 

IN 

DUT 


235 

5 




SP721 

236 


100 

80 

60 

40 

20 

T A = 25 o C 

SINGLE PULSE 

0 

600 800 1000 1200 



CURVE 

+V CC 

INPUT 

DRIVERS 

OR 

SIGNAL 

SOURCES 

SP721 

IN 1 - 3 


2.5 


2 

1.5 

1 

0.5 

SP721 INPUT PROTECTION CIRCUIT (1 OF 6 SHOWN) 

0 

T A = 25 o C 

SINGLE PULSE 



V FWD 

I FWD 

0 1 2 3 



CURVE 



IN 5 - 7 

V- 

+V CC 

LINEAR OR 

DIGITAL IC 

INTERFACE 

V+ 

TO +V CC



SP721 




SP721’s ability to withstand a wide range of peak current pulses vs time. 

The circuit used to generate current pulses is shown in Figure 5. 








The maximum peak input current capability is dependent on the ambient 

temperature, improving as the temperature is reduced. Peak current 

curves are shown for ambient temperatures of 25 o C and 105 o C and a 15V 

power supply condition. The safe operating range of the transient peak 

current should be limited to no more than 75% of the measured overstress 

level for any given pulse width as shown in the curves of Figure 6. 

Note that adjacent input pins of the SP721 may be paralleled to improve 

current (and ESD) capability. The sustained peak current capability is 

increased to nearly twice that of a single pin. 


7 

6 

5 

4 

3 

2 

1 

T A = 105 o C 

T A = 25 o C 


+ 

VX - 

R 1 

VOLTAGE 

PROBE 


VX ADJ. 10V/A TYPICAL 

C1 ~ 100µF 

(+) 

1 

2 

3 

4 



CURRENT 

SENSE 

IN 

IN 

IN 

V- 

SP721 







V+ TO V- SUPPLY = 15V 

0 

0.001 0.01 0.1 1 


10 

V+ 

IN 

IN 

IN 

8 

7 

6 

5 

(-) 

C1 

100 1000 

FIGURE 6. SP721 TYPICAL SINGLE PULSE PEAK CURRENT CURVES SHOWING THE MEASURED POINT OF OVERSTRESS IN 

AMPERES vs PULSE WIDTH TIME IN MILLISECONDS 

+ 

- 

237 

5 




SP721 

Dual-In-Line Plastic Packages (PDIP) 

INDEX 

AREA 

BASE 

PLANE 

SEATING 

PLANE 

D1 

B1 

238 

-A- 

N 

1 2 3 N/2 

B 

D 

e 

D1 

E1 

-B- 

-C- 

A 1 

A2 

L 

A 

e C 

0.010 (0.25) M C A B S 

NOTES: 

1. Controlling Dimensions: INCH. In case of conflict between 

English and Metric dimensions, the inch dimensions control. 


3. Symbols are defined in the “MO Series Symbol List” in Section 

2.2 of Publication No. 95. 

4. Dimensions A, A1 and L are measured with the package seated 

in JEDEC seating plane gauge GS-3. 


Mold flash or protrusions shall not exceed 0.010 inch 

(0.25mm). 





8. B1 maximum dimensions do not include dambar protrusions. 

Dambar protrusions shall not exceed 0.010 inch (0.25mm). 


10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, 

E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch 

(0.76 - 1.14mm). 

E 

C L 

e A 

C 

e B 


E8.3 (JEDEC MS-001-BA ISSUE D) 




A - 0.210 - 5.33 4 

A1 0.015 - 0.39 - 4 

A2 0.115 0.195 2.93 4.95 - 

B 0.014 0.022 0.356 0.558 - 

B1 0.045 0.070 1.15 1.77 8, 10 

C 0.008 0.014 0.204 0.355 - 

D 0.355 0.400 9.01 10.16 5 

D1 0.005 - 0.13 - 5 

E 0.300 0.325 7.62 8.25 6 

E1 0.240 0.280 6.10 7.11 5 

e 0.100 BSC 2.54 BSC - 

eA 0.300 BSC 7.62 BSC 6 

eB - 0.430 - 10.92 7 

L 0.115 0.150 2.93 3.81 4 

N 8 8 9



SP721 

Small Outline Plastic Packages (SOIC) 

N 

INDEX 

AREA 

1 2 3 

-A- 

e 

D 

B 

E 

-C- 

-B- 

SEATING PLANE 

0.25(0.010) M C A M B S 

A 

H 

A1 

µ 

0.25(0.010) M B M 

0.10(0.004) 

L 

h x 45 o 

NOTES: 








flash and protrusions shall not exceed 0.25mm (0.010 inch) per 

side. 






9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater 

above the seating plane, shall not exceed a maximum value of 

0.61mm (0.024 inch). 

10. Controlling dimension: MILLIMETER. Converted inch dimensions 

are not necessarily exact. 

C 


M8.15 (JEDEC MS-012-AA ISSUE C) 




A 0.0532 0.0688 1.35 1.75 - 

A1 0.0040 0.0098 0.10 0.25 - 

B 0.013 0.020 0.33 0.51 9 

C 0.0075 0.0098 0.19 0.25 - 

D 0.1890 0.1968 4.80 5.00 3 

E 0.1497 0.1574 3.80 4.00 4 

e 0.050 BSC 1.27 BSC - 

H 0.2284 0.2440 5.80 6.20 - 

h 0.0099 0.0196 0.25 0.50 5 

L 0.016 0.050 0.40 1.27 6 

N 8 8 7 

0 o 

8 o 

0 o 

8 o 

µ 

- 

239 

5 




SP723 


over-voltage protection of sensitive input circuits. The SP723 has 2 

protection SCR/Diode device structures per input. There are a total of 6 

available inputs that can be used to protect up to 6 external signal or bus 

lines. Over-voltage protection is from the IN (Pins 1 - 3 and Pins 5 - 7) 

to V+ or V-. 


+V BE diode threshold above V+ (Pin 8) or a -V BE diode threshold below 

V- (Pin 4). From an IN input, a clamp to V+ is activated if a transient 

pulse causes the input to be increased to a voltage level greater than 

one V BE above V+. A similar clamp to V- is activated if a negative pulse, 

one V BE less than V-, is applied to an IN input. 

Refer to Fig 1 and Table 1 for further details. Refer to Application Note 

AN9304 and AN9612 for further detail. 


PART 

NUMBER 

Functional Diagram 

240 

TEMP. RANGE 

( o C) PACKAGE PKG. NO. 

Min. Order 

Qty. 




Tape and Reel 

M8.15 2500 

V+ 

IN 

V- 

8 

1 

4 

IN 2 

3, 5-7 

IN 

Features 


• ESD Interface per HBM Standards 

- IEC 61000-4-2, Direct Discharge . . . . . . . . . . . . . . . . . 8kV (Level 4) 


- MIL-STD-3015.7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25kV 

• Peak Current Capability 

- IEC 61000-4-5 8/20µs Peak Pulse Current. . . . . . . . . . . . . . . . . ±7A 

- Single Transient Pulse, 100s Pulse Width. . . . . . . . . . . . . . . . . . ±4A 


- Single-Ended Voltage Range to . . . . . . . . . . . . . . . . . . . . . . . . +30V 

- Differential Voltage Range to. . . . . . . . . . . . . . . . . . . . . . . . . . . ±15V 

• Fast Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2ns Risetime 

• Low Input Leakages . . . . . . . . . . . . . . . . . . . . . . . . 2nA at 25 o C Typical 




Applications 





Pinout 

IN 

IN 

IN 

V- 

1 

2 

3 

4 

SP723 

(PDIP, SOIC) 

TOP VIEW 

8 

7 

6 

5 

V+ 

IN 

IN 

IN



SP723 


Continuous Supply Voltage, (V+) - (V-). ........................+35V 

Forward Peak Current, I IN to V CC , I IN to GND 

(Refer to Figure 6). .................................±4A, 100µs 

Peak Pulse Current, 8/20µs...................................±7A 





NOTE: 


Electrical Specification T A =40 o C to 105 o C, V IN = 0.5V CC , Unless Otherwise Specified 


ESD capability is dependent on the application and defined test 

standard.The evaluation results for various test standards and methods 

based on Figure 1 are shown in Table 1. 

The SP723 has a Level 4 HBM capability when tested as a device to the 

IEC 61000-4-2 standard. Level 4 specifies a required capability greater 

than 8kV for direct discharge and greater than 15kV for air discharge. 

For the “Modified” MIL-STD-3015.7 condition that is defined as an “incircuit” 

method of ESD testing, the V+ and V- pins have a return path to 

ground and the SP723 ESD capability is typically greater than 25kV from 

100pF through 1.5kΩ. By strict definition of MIL-STD-3015.7 using “pinto-pin” 

device testing, the ESD voltage capability is greater than 10kV. 

For the SP723 EIAJ IC121 Machine Model (MM) standard, the ESD capability 

is typically greater than 2kV from 200pF with no series resistance. 



Thermal Resistance (Typical, Note 1) θJA ( oC/W) PDIP Package . ...........................................160 

SOIC Package . ..........................................170 

Storage Temperature Range . ...........................-65oC to 150oC Maximum Junction Temperature..............................150oC Lead Temperature (Soldering 10s). ........................... 300oC (SOIC - Lead Tips Only) 


IEC 1000-4-2 

(Level 4) 

HBM, Air Discharge 330Ω 150pF 15kV 


MIL-STD-3015.7 Modified HBM 1.5kΩ 100pF 25kV 



H.V. 

SUPPLY 

°±V D 


CHARGE 

SWITCH 

R 1 

C D 

R D 

IEC 1000-4-2: R1 50 to 100MΩ 

MIL-STD-3015.7: R1 1 to 10MΩ 

DISCHARGE 

SWITCH 

IN 

DUT 


241 

5 




SP723 


242 

200 

160 

120 

80 

40 

T A = 25 o C 

SINGLE PULSE 

0 

600 800 1000 1200 



CURVE 

+V CC 

INPUT 

DRIVERS 

OR 

SIGNAL 

SOURCES 

SP723 

IN 1 - 3 




5 

4 

3 

2 

1 

T A = 25 o C 

SINGLE PULSE 



V FWD 

I FWD 

0 

0 1 2 3 



CURVE 



IN 5 - 7 

V- 

+V CC 

LINEAR OR 

DIGITAL IC 

INTERFACE 

V+ 

TO +V CC



SP723 




SP723’s ability to withstand a wide range of peak current pulses vs time. 

The circuit used to generate current pulses is shown in Figure 5. 








The maximum peak input current capability is dependent on the ambient 

temperature, improving as the temperature is reduced. Peak current 

curves are shown for ambient temperatures of 25 o C and 105 o C and a 15V 

power supply condition. The safe operating range of the transient peak 

current should be limited to no more than 75% of the measured overstress 

level for any given pulse width as shown in the curves of Figure 6. 

Note that adjacent input pins of the SP723 may be paralleled to improve 


increased to nearly twice that of a single pin. 


14 

12 

10 

8 

6 

4 

2 

T A = 105 o C 

T A = 25 o C 

0 

0.001 0.01 0.1 1 


+ 

VX - 


R 1 

VOLTAGE 

PROBE 



C1 ~ 100µF 

(+) 



CURRENT 

SENSE 

1 

2 

3 

4 

IN 

IN 

IN 

V- 

V+ 

IN 

SP723 

IN 

IN 








FIGURE 6. SP723 TYPICAL SINGLE PULSE PEAK CURRENT CURVES SHOWING THE MEASURED POINT OF OVERSTRESS IN 

AMPERES vs PULSE WIDTH TIME IN MILLISECONDS 

10 

8 

7 

6 

5 

(-) 

C1 

100 1000 

+ 

- 

243 

5 




SP723 

Dual-In-Line Plastic Packages (PDIP) E8.3 (JEDEC MS-001-BA ISSUE D) 


INDEX 

AREA 

BASE 

PLANE 

SEATING 

PLANE 

D1 

B1 

244 

-A- 

N 

1 2 3 N/2 

B 

D 

e 

D1 

E1 

-B- 

-C- 

A 1 

A2 

L 

A 

e C 

0.010 (0.25) M C A B S 

NOTES: 

1. Controlling Dimensions: INCH. In case of conflict between 

English and Metric dimensions, the inch dimensions control. 


3. Symbols are defined in the “MO Series Symbol List” in Section 

2.2 of Publication No. 95. 

4. Dimensions A, A1 and L are measured with the package seated 

in JEDEC seating plane gauge GS-3. 


Mold flash or protrusions shall not exceed 0.010 inch 

(0.25mm). 





8. B1 maximum dimensions do not include dambar protrusions. 

Dambar protrusions shall not exceed 0.010 inch (0.25mm). 


10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, 

E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch 

(0.76 - 1.14mm). 

E 

C L 

e A 

C 

e B 




A - 0.210 - 5.33 4 

A1 0.015 - 0.39 - 4 

A2 0.115 0.195 2.93 4.95 - 

B 0.014 0.022 0.356 0.558 - 

B1 0.045 0.070 1.15 1.77 8, 10 

C 0.008 0.014 0.204 0.355 - 

D 0.355 0.400 9.01 10.16 5 

D1 0.005 - 0.13 - 5 

E 0.300 0.325 7.62 8.25 6 

E1 0.240 0.280 6.10 7.11 5 

e 0.100 BSC 2.54 BSC - 

eA 0.300 BSC 7.62 BSC 6 

eB - 0.430 - 10.92 7 

L 0.115 0.150 2.93 3.81 4 

N 8 8 9



SP723 

Small Outline Plastic Packages (SOIC) M8.15 (JEDEC MS-012-AA ISSUE C) 


N 

INDEX 

AREA 

1 2 3 

-A- 

e 

D 

B 

E 

-C- 

-B- 

SEATING PLANE 

0.25(0.010) M C A M B S 

A 

H 

A1 

µ 

0.25(0.010) M B M 

0.10(0.004) 

L 

h x 45 o 

NOTES: 








flash and protrusions shall not exceed 0.25mm (0.010 inch) per 

side. 






9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater 

above the seating plane, shall not exceed a maximum value of 

0.61mm (0.024 inch). 

10. Controlling dimension: MILLIMETER. Converted inch dimensions 

are not necessarily exact. 

C 




A 0.0532 0.0688 1.35 1.75 - 

A1 0.0040 0.0098 0.10 0.25 - 

B 0.013 0.020 0.33 0.51 9 

C 0.0075 0.0098 0.19 0.25 - 

D 0.1890 0.1968 4.80 5.00 3 

E 0.1497 0.1574 3.80 4.00 4 

e 0.050 BSC 1.27 BSC - 

H 0.2284 0.2440 5.80 6.20 - 

h 0.0099 0.0196 0.25 0.50 5 

L 0.016 0.050 0.40 1.27 6 

N 8 8 7 

0o 8o 0o 8o µ 

- 

245 

5 



SCR Diode Array for ESD and Transient Overvoltage Protection 

SP724 

The SP724 is a quad array of transient voltage clamping circuits designed 

to suppress ESD and other transient over-voltage events. The SP724 is 

used to help protect sensitive digital or analog input circuits on data, 

signal, or control lines operating on power supplies up to 20VDC. 

The SP724 is comprised of bipolar SCR/diode structures to protect up 

to four independent lines by clamping transients of either polarity to the 

power supply rails. The SP724 offers very low leakage (1nA Typical) and 

low input capacitance (3pF Typical). Additionally, the SP724 is rated to 

withstand the IEC 61000-4-2 ESD specification for both contact and air 

discharge methods to level 4. 

The SP724 is connected to the sensitive input line and its associated 

power supply lines. Clamping action occurs during the transient pulse, 

turning on the diode and fast triggering SCR structures when the voltage 

on the input line exceeds one V BE threshold above the V+ supply (or 

one V BE threshold below the V- supply). Therefore, the SP724 operation 

is unaffected by poor power supply regulation or voltage fluctuations 

within its operating range. 


PART TEMP. RANGE 

Min. Order 

NUMBER ( Qty. 

o C) PACKAGE PKG. NO. 

SP724AHT -40 to 105 Tape and Reel 

Pinout 

246 

SP724 

(SOT-23) 

TOP VIEW 

6 5 4 

1 2 3 

P6.064 3000 

Features 


• An Array of 4 SCR/Diode Pairs in 6-Lead SOT-23 

• ESD Capability per HBM Standards 

- IEC 61000-4-2, Direct Discharge . . . . . . . . . . . . . . . . . 8kV (Level 4) 


- MIL STD 3015.7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >8kV 

• Input Protection for Applications with Power Supplies Up to +20V 

(Single-Ended Voltage), and ±10V (Differential Voltage) 

• Peak Current Capability 

• IEC 61000-4-5 (8/20µs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±3A 

• Single Pulse, 100µs Pulse Width . . . . . . . . . . . . . . . . . . . . . . . ±2.2A 

• Low Input Leakage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1nA Typical 



Applications 






V+ 5 

IN 

V- 

1 

2 

3, 4 AND 6 

IN 

NOTES: 

1. The design of the SP724 SCR/Diode ESD Protection Arrays is 

covered by Littelfuse patent 4567500. 

2. The full ESD capability of the SP724 is achieved when wired in a 

circuit that includes connection to both the V+ and V- pins. When 

handling individual devices, follow proper procedures for 

electrostatic discharge.



SP724 


Continuous Supply Voltage, (V+) - (V-). ........................+20V 

Forward Peak Current, IIN to VCC , GND 

(Refer to Figure 6). ................................±2.2A, 100µs 

ESD Ratings and Capability - See Figure 1, Table 1 



Thermal Resistance (Typical, Note 3) θJA ( oC/W) SOT Package . ........................................... 220 

Maximum Storage Temperature Range.......................-65oC to 150oC Maximum Junction Temperature . .............................150oC Maximum Lead Temperature (Soldering 10s) . ........................300oC (SOT - Lead Tips Only) 

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these 

or any other conditions above those indicated in the operational sections of this specification is not implied. 

NOTE: 


Electrical Specifications T A = -40 o C to 105 o C, V IN = 0.5V CC , Unless Otherwise Specified 



VSUPPLY = [(V+) - (V-)] (Notes 4, 5) 

Forward Voltage Drop 

VSUPPLY 1 - 20 V 

IN to V- VFWDL IIN = 1A (Peak Pulse) - 2 - V 

IN to V+ VFWDH - 2 - V 

Input Leakage Current IIN -10 1 10 nA 

Quiescent Supply Current IQUIESCENT V+ = 20V, V- = GND - - 100 nA 

Equivalent SCR ON Threshold (Note 6) - 1.1 - V 

Equivalent SCR ON Resistance VFWD/IFWD (Note 6) - 1.0 - Ω 

Input Capacitance 

NOTES: 

CIN - 3 - pF 

4. In automotive and other battery charging systems, the SP724 power supply lines should be externally protected for load dump and reverse battery. When 

the V+ and V- Pins are connected to the same supply voltage source as the device or control line under protection, a current limiting resistor should be 

connected in series between the external supply and the SP724 supply pins to limit reverse battery current to within the rated maximum limits. 

5. Bypass capacitors of typically 0.01µF or larger should be connected closely between the V+ and V- Pins for all applications. 

6. Refer to the Figure 3 graph for definitions of equivalent “SCR ON Threshold” and “SCR ON Resistance”. These characteristics are given here 

for information to determine peak current and dissipation under EOS conditions. 

ESD Rating 

ESD rating is dependent on the defined test standard. The evaluation 

results for various test standards and methods based on Figure 1 are 

shown in Table 1.3 

The SP724 has a Level 4 rating when tested to the IEC 61000-4-2 

Human Body Model (HBM) standard and connected in a circuit in which 

the V+ and V- pins have a return path to ground. Level 4 specifies a 

required capability greater than 8kV for direct discharge and greater than 

15kV for air discharge. 

The “Modified” MIL-STD-3015.7 condition is defined as an “in-circuit” 

method of ESD testing, the V+ and V- pins have a return path to 

ground.The SP724 ESD capability is greater than 8kV with 100pF 

discharged through 1.5kΩ. By strict definition of the standard MIL- 

STD-3015.7 method using “pin-to-pin” device testing, the ESD voltage 

capability is greater than 2kV. 

For the SP724 EIAJ IC121 Machine Model (MM) standard, the ESD capability 

is typically greater than 1.8kV with 200pF discharged through 0kΩ. 

The Charged Device model is based upon the self-capacitance of the 

SOT-23 package through 0kΩ. 




(Level 4) 


MIL-STD-3015.7 Modified HBM 1.5kΩ 100pF 8kV† 


EIAJ IC121 Machine Model 0kΩ 200pF 400V 

US ESD DS 5.3 Charged Device Model 0kΩ NA 3kV 

†Upper limit of laboratory test set. 

H.V. 

SUPPLY 

±V D 

CHARGE 

SWITCH 

R 1 

C D 

R D 

DISCHARGE 

SWITCH 

IEC 1000-4-2: R1 50 to 100MΩ 

MIL STD 3015.7: R11 to 10MΩ 

IN 

DUT 


247 

5 




SP724 


248 

200 

160 

120 

80 

40 

T A = 25 o C 

SINGLE PULSE 

0 

600 800 1000 1200 



CURVE 

+V CC 

INPUT 

DRIVERS 

OR 

SIGNAL 

SOURCES 

SP724 

IN 1, 3, 4 AND 6 




5 

4 

3 

2 

1 

T A = 25 o C 

SINGLE PULSE 



0 

0 1 2 3 



CURVE 

V- 

+V CC 

LINEAR OR 

DIGITAL IC 

INTERFACE 

V+ 

TO +V CC 



0.01µF



SP724 

Peak Transient Current Capability for Long Duration Surges 

The peak transient current capability is inversely proportional to the width 

of the current pulse. Testing was done to fully evaluate the SP724’s 

ability to withstand long duration current pulses using the circuit of 

Figure 5. Figure 6 shows the point of overstress as defined by increased 

leakage in excess of the data sheet published limits. The safe operating 

range of the transient peak current should be limited to no more than 

75% of the measured overstress level for any given pulse width as 

shown in the curve of Figure 6. 





to the ground reference of the current pulse generator.) 

Note that two input pins of the SP724 may be paralleled to improve 



C1 ~ 100µF 

increased to nearly twice that of a single pin. FIGURE 5. TYPICAL SP724 PEAK CURRENT TEST CIRCUIT 



8 

7 

6 

5 

4 

3 

2 

1 


+ 

VX - 

R 1 ~ 10Ω TYPICAL 

0 

0.001 0.01 0.1 1 

SQUARE WAVE PULSE WIDTH (ms) 

R 1 

(+) 

VOLTAGE 

PROBE 



CURRENT 

SENSE 

FIGURE 6. SP724 TYPICAL NONREPETITIVE PEAK CURRENT PULSE CAPABILITY 

10 

1 2 3 

SP724 

6 5 4 

NOTE: TO ENSURE SAFE OPERATION LIMIT THE 

MAXIMUM PEAK CURRENT FOR A GIVEN 


OF THE VALUES SHOWN. 

TA = 25 


oC (-) 

C 1 

100 1000 

+ 

- 

249 

5 




SP724 

Small Outline Transistor Plastic Packages (SOT23-6) 

250 


P6.064 

6 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE 



A 0.036 0.057 0.90 1.45 - 

A1 0.000 0.0059 0.00 0.15 - 

A2 0.036 0.051 0.90 1.30 - 

b 0.0138 0.0196 0.35 0.50 - 

C 0.0036 0.0078 0.09 0.20 - 

D 0.111 0.118 2.80 3.00 3 

E 0.103 0.118 2.60 3.00 - 

E1 0.060 0.068 1.50 1.75 3 

e 0.0374 Ref 0.95 Ref - 

e1 0.0748 Ref 1.90 Ref - 

L 0.004 0.023 0.10 0.60 4, 5 

N 6 6 6 

0 o 

10 o 

0 o 

10 o - 

Rev. 1 2/98



SP724 

SOT23-6 

8mm TAPE AND REEL 

ACCESS HOLE 

180mm 

14.4mm 

13mm 

60mm 

8.4mm 

8mm 


1.5mm 

DIA. HOLE 

COVER TAPE 

4.0mm 

4.0mm 

2.0mm 

SOT-23 (8mm POCKET PITCH) 

USER DIRECTION OF FEED 

GENERAL INFORMATION 

1. 3000 PIECES PER REEL. 

2. ORDER IN MULTIPLES OF FULL REELS ONLY . 

3. MEETS EIA-481 REVISION "A" SPECIFICATIONS. 

C L 

PIN 1 

1.75mm 

Rev. 0 2/99 

251 

5 



Notes and Drawings 

252 

www.littelfuse.com

TVS Diode Arrays

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