GAL22V10

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SWITCHING WAVEFORMS INPUT or I/O FEEDBACK COMBINATORIAL OUTPUT INPUT or I/O FEEDBACK OUTPUT CLK Combinatorial Output VALID INPUT tpd Input or I/O to Output Enable/Disable INPUT or I/O FEEDBACK DRIVING SP CLK REGISTERED OUTPUT t dis tw h twl Clock Width 1/ fmax (w/o fdbk) tsu th Synchronous Preset tco ten tspr Specifications <strong>GAL22V10</strong> INPUT or I/O FEEDBACK CLK REGISTERED OUTPUT CLK CLK REGISTERED FEEDBACK INPUT or I/O FEEDBACK DRIVING AR REGISTERED OUTPUT VALID INPUT Registered Output 10 1996 Data Book tsu th tco 1/ fmax (external fdbk) 1/ fmax (internal fdbk) tcf tsu fmax with Feedback tarw tar Asynchronous Reset tarr
fmax DESCRIPTIONS LOGIC ARRAY tsu fmax with External Feedback 1/(tsu+tco) Note: fmax with external feedback is calculated from measured tsu and tco. LOGIC ARRAY tsu + th CLK REGISTER SWITCHING TEST CONDITIONS Input Pulse Levels GND to 3.0V Input Rise and -5 1.5ns 10% – 90% Fall Times -7/-10 2.0ns 10% – 90% -15/-20/-25 3ns 10% – 90% Input Timing Reference Levels 1.5V Output Timing Reference Levels 1.5V Output Load See Figure 3-state levels are measured 0.5V from steady-state active level. Output Load Conditions (see figure) CLK Test Condition R1 R2 CL A 300Ω 390Ω 50pF B Active High ∞ 390Ω 50pF Active Low 300Ω 390Ω 50pF C Active High ∞ 390Ω 5pF Active Low 300Ω 390Ω 5pF tco REGISTER fmax with No Feedback Note: fmax with no feedback may be less than 1/(twh + twl). This is to allow for a clock duty cycle of other than 50%. Specifications <strong>GAL22V10</strong> LOGIC ARRAY fmax with Internal Feedback 1/(tsu+tcf) Note: tcf is a calculated value, derived by subtracting tsu from the period of fmax w/internal feedback (tcf = 1/fmax - tsu). The value of tcf is used primarily when calculating the delay from clocking a register to a combinatorial output (through registered feedback), as shown above. For example, the timing from clock to a combinatorial output is equal to tcf + tpd. FROM OUTPUT (O/Q) UNDER TEST R 2 tcf tpd +5V TEST POINT 11 1996 Data Book CLK REGISTER C * L *C L INCLUDES TEST FIXTURE AND PROBE CAPACITANCE R 1
Page 1 and 2: FEATURES • HIGH PERFORMANCE E2CMO
Page 3 and 4: OUTPUT LOGIC MACROCELL (OLMC) The G
Page 5 and 6: GAL22V10 LOGIC DIAGRAM / JEDEC FUSE
Page 7 and 8: AC SWITCHING CHARACTERISTICS Over R
Page 9: AC SWITCHING CHARACTERISTICS PARAM.
Page 13 and 14: POWER-UP RESET Circuitry within the
Page 15 and 16: Specifications GAL22V10 GAL22V10C-5
Page 17 and 18: Specifications GAL22V10 GAL22V10B-7
Page 19 and 20: Specifications GAL22V10 GAL22V10B-1
Page 21: Copyright © 1996 Lattice Semicondu

GAL22V10

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