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(12) PATENT APPLICATION PUBLICATION
(19) INDIA
(21) Application No.1943/DEL/2009 A
(22) Date of filing of Application :17/09/2009 (43) Publication Date : 18/06/2010
(54) Title of the invention : HIGH VOLTAGE VERTICAL TRANSISTOR WITH A VARIED WIDTH SILICON PILLAR
(51) International classification :H01L1/00
(31) Priority Document No :12/284,086
(32) Priority Date :18/09/2008
(71)Name of Applicant :
1)POWER INTEGRATIONS INC
Address of Applicant :5245 HELLYER AVENUE, SAN
JOSE, CA 95138 USA.
(72)Name of Inventor :
1)BANERJEE SUJIT
2)PARTHASARATHY VIJAY
3)ZHU LIN
(33) Name of priority country :U.S.A.
(86) International Application No
:NA
Filing Date
:NA
(87) International Publication No :NA
(61) Patent of Addition to Application Number :NA
Filing Date
:NA
(62) Divisional to Application Number
:NA
Filing Date
:NA
(57) Abstract :
In one embodiment, a vertical HVFET includes a pillar of semiconductor material a pillar of semiconductor material arranged in a
loop layout having at least two substantially parallel and substantially linear fillet sections each having a first width, and at least two
rounded sections, the rounded sections having a second width narrower than the first width, a source region of a first conductivity type
being disposed at or near a top surface of the pillar, and a body region of a second conductivity type being disposed in the pillar
beneath the source region. First and second dielectric regions are respectively disposed on opposite sides of the pillar, the first
dielectric region being laterally surrounded by the pillar, and the second dielectric region laterally surrounding the pillar. First and
second field plates are respectively disposed in the first and second dielectric regions.
No. of Pages : 27 No. of Claims : 24
The Patent Office Journal 18/06/2010 15855