System-on-Chip Design Flow
System-on-Chip Design Flow
System-on-Chip Design Flow
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ASIC design flow interfaces<br />
DESIGN TEAM CUSTOMER ASIC VENDOR<br />
Requirement spec<br />
Data sheet for acceptance<br />
Verificati<strong>on</strong> for acceptance<br />
(modeler/testbench/simul.results)<br />
Technical info for quotati<strong>on</strong><br />
Library & tools<br />
Netlist, test vectors, arch.plan<br />
Backannotati<strong>on</strong> from P&R<br />
Acceptance for prototype producti<strong>on</strong> (sign off)<br />
ASIC quotati<strong>on</strong><br />
Prototype ASICs (/risk producti<strong>on</strong>)<br />
Prototype acceptance<br />
Mass producti<strong>on</strong> ASICs<br />
26.03.2003 Jouni Tomberg / TUT 10
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