System-on-Chip Design Flow
System-on-Chip Design Flow
System-on-Chip Design Flow
Create successful ePaper yourself
Turn your PDF publications into a flip-book with our unique Google optimized e-Paper software.
<strong>Design</strong> Bottlenecks * Source EETIMES EDA 2000 Survey<br />
Simulati<strong>on</strong>/<strong>Design</strong> Verificati<strong>on</strong> 51%<br />
<strong>Design</strong> Creati<strong>on</strong><br />
Place & Route<br />
Post Layout Optimizati<strong>on</strong><br />
Parasitic Extracti<strong>on</strong><br />
<str<strong>on</strong>g>System</str<strong>on</strong>g> or <str<strong>on</strong>g>System</str<strong>on</strong>g>-<strong>on</strong>-<strong>Chip</strong><br />
Layout Versus Schematic(LVS)<br />
<strong>Design</strong> Rule Check (DRC)<br />
Static Timing Analysis<br />
Synthesis<br />
Delay Calculati<strong>on</strong><br />
26.03.2003 Jouni Tomberg / TUT 12<br />
17%<br />
17%<br />
17%<br />
16%<br />
15%<br />
13%<br />
26%<br />
32%<br />
32%<br />
Base = 545<br />
0% 10% 20% 30% 40% 50% 60%<br />
50 -70 % of project effort devoted to design verificati<strong>on</strong>!
Change language