SIMPLE PLL-BASED TRUE RANDOM NUMBER ... - KEMT FEI TUKE

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Our aim was to find a solution completely embedded in a digital circuit. These circuits are well suited for implementation of so called pseudo-random number generators. However, pseudo-random number generators cannot provide sufficient security, because they are predictable. Digital circuits include only limited sources of randomness, e. g. metastability, frequency of a free-running oscillator, clock jitter, etc. Usually, reliable generators based on the metastability and/or frequency instability are difficult to implement and they are not secure enough for cryptographic applications. The entropy increase is not sufficiently high in some cases, so the output of generator can be predicted [4]. In another case [5] off-chip components are required what decreases a cryptographic security of the implementation. In contrast with these methods, in [6] we have proposed a novel method of randomness extraction based on two rationally related synthesized clock signals. It was shown that it is perfectly suited for modern FPLDs with the internal analog phase-locked loop (PLL) circuitry (e.g. Apex or Stratix FPLDs from Altera). The generator provided random data with only small deviations from ideal one. In this paper we present a modified version of our generator [6] having simplified structure and higher data rate. It is based on an extended knowledge of jitter features obtained by measurements in real conditions on Altera development boards. 2 The PLL-synthesized clock jitter 2.1 Analog PLLs embedded in digital circuits New digital VLSI circuits use advanced clock generation and distribution circuitry based on embedded analog PLLs [7], [8], [9], [10]. A simplified block diagram of one analog based PLL block available in advanced digital circuits is depicted in Figure 1. Each PLL block can provide at least one synthesized clock signal with frequency F OUT : m KM FOUT = FIN = FIN (1) n× k KD where F IN is the frequency of the external input clock source. Reference-, feedback- and post-divider values n, m and k can vary from one to several hundreds in FPGAs [9], [10], or to several thousands in ASICs [8]. :n Input Clock FIN Phase Frequency Detector :m Charge Pump & Loop VCO :k Filter Output Clock ClockShift Circuitry FOUT = FIN m n × k Figure 1: Simplified block diagram of an embedded PLL circuitry 2.2 Jitter of PLL synthesized clock signals In analog PLLs, a noise causes the Voltage Controlled Oscillator (VCO) to fluctuate in frequency. Other frequency fluctuations are caused by variations of supply voltage, temperature and by a noisy environment. The internal control circuitry adjusts the VCO
ack to the specified frequency, but a certain part of the fluctuations caused by nondeterministic noise cannot be compensated for and is seen as a clock jitter. The size of the intrinsic jitter depends on the quality factor Q of the VCO, on the bandwidth of the Loop Filter and on the so-called pattern jitter introduced by the Phase Frequency Detector. It is often given in peak-to-peak value or 1-sigma (or RMS) value. 1sigma value of the jitter ( σ jit ) depends on the technology and the configuration of the PLL and it can range from 3.5 ps to 10 ps for ASICs [8] up to 50 ps for FPGAs [9], [10]. Since the technology of the PLL and the quality of the VCO is usually defined, a user can change the output jitter by modification of divider values and filter bandwidth. For example the jitter in an Apex FPLD has 1-sigma value of σ jit ≈15.9 ps for a F OUT = 66.6 MHz clock signal and multiplication factor 2 [11]. These results were acquired under “ideal conditions”, with only a minimal amount of FPLD resources occupied and minimal input/output activities. Our last measurements (cf. in subsection 2.3) show that the clock jitter in an Apex FPLD is significantly higher (about 140 ps ) for higher multiplication factors and when internal FPLD flip-flops are switching on different clock frequencies. 2.3 Jitter size measurement Since the knowledge of the jitter size and its statistical features is crucial for correct settings of the TRNG parameters, several measurements have been made for different configurations of the PLL (different values KM and KD ). We used Agilent Infiniium DCA 86100B wide bandwidth oscilloscope and the Nios development board [12] with Apex EP20K200 device. The 1-sigma value of the jitter measured at the output of the PLL has achieved values σ jit ≈ 32 ps for FIN = 33. 3 MHz and KM K D = 21. For ratios KM K D = 32,43,54,65… the 1-sigma value was in the range σ jit ≈47 −64ps and the jitter has approximately Gaussian distribution as it is illustrated in Figure 2a) for configuration M D 65 = K K . However, for M D 157 48 = K K used in [6], the jitter was σ jit ≈140 ps and it exhibited two peaks with a total size of 600 ps (peak-to-peak). The obtained jitter distribution is depicted in Figure 2b) and it is compatible with a reference measurement made by Xilinx on Altera FPLDs [11], where a two-peak jitter distribution has been documented. Since the jitter included in the clock signal in real conditions was significantly higher than that documented by Altera (note, that Altera has used the same kind of development board, only K M and KD parameters were different), we could significantly reduce the generator complexity. As far as K M and K D parameters are chosen properly, the proposed method is insensitive to the jitter distribution (see section 3 and [6]). a) b) Figure 2: The jitter probability distribution for a) 65 M D K K = b) K K = 157 48 M D
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Page 5 and 6: Thanks to the measurements we got t
Page 7 and 8: prove even further the quality of t

SIMPLE PLL-BASED TRUE RANDOM NUMBER ... - KEMT FEI TUKE

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