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SIMPLE PLL-BASED TRUE RANDOM NUMBER ... - KEMT FEI TUKE

SIMPLE PLL-BASED TRUE RANDOM NUMBER ... - KEMT FEI TUKE

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internal random process. The randomness of the sequence of numbers has been extensively<br />

tested and only extremely small differences from an ideal TRNG have been detected.<br />

The proposed solution is very cheap, it uses a very small number of logic resources and<br />

it is faster than comparable methods. Although the functionality of the proposed solution<br />

has been demonstrated for Altera Apex family, the same principle can be used for all recent<br />

high-performance ASICs or FPLDs that include an on-chip reconfigurable analog <strong>PLL</strong> for<br />

clock synthesis.<br />

In the future we plan a deeper research of the jitter and its measurement, as its statistical<br />

features directly affect the statistical features of the output random sequence.<br />

Acknowledgments<br />

This work has been done in the frame of the project CryptArchi included in the French<br />

national program ACI Cryptologie and Slovak scientific project VEGA 1/1057/04.<br />

References<br />

[1] T. Jennewein, U. Achleitner, G. Weihs, H. Weinfurter, A. Zeilinger, “A fast and compact quantum random<br />

number generator”, Rev. Sci. Inst. 71, 1675-1680 (2000)<br />

[2] J. Walker, “Hotbits: Genuine random numbers, generated by radioactive decay”, online at<br />

www.fourmilab.ch/hotbits<br />

[3] B. Jun, P. Kocher, "The INTEL Random Number Generator", Cryptography Research, Inc., White Paper<br />

prepared for Intel Corporation, April 1999, pp.1-8, www.intel.com<br />

[4] M. Dichtl, “How to Predict the Output of a Hardware Random Number Generator”, In C.D. Walter, C. K.<br />

Koc, Ch. Paar (Eds.): CHES 2003, LNCS 2779, Springer, Berlin, 2003, pp.181-188<br />

[5] K.H. Tsoi, K.H. Leung, P.H. Leong, “Compact FPGA-based True and Pseudo Random Number<br />

Generators”, Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines<br />

(FCCM), California USA, 2003, pp.51-61<br />

[6] V. Fischer, M. Drutarovský, “True Random Number Generator Embedded in Reconfigurable Hardware”,<br />

In B.S.Kaliski Jr. et al. (Eds.): CHES 2002, LNCS 2523, Springer, Berlin, 2003, pp.415-430<br />

[7] J. G. Maneatis, “Selecting <strong>PLL</strong>s for ASIC Applications Requires Tradeoffs”, Planet Analog Magazine<br />

9/2003, www.planetanalog.com<br />

[8] “XpressArray High Density 0.18um Structured ASIC”, WEB page of the AMI Semiconductors Company,<br />

www.amis.com<br />

[9] “Using the ClockLock & ClockBoost <strong>PLL</strong> Features in Apex Devices”, Altera Application Note 115, v.2.3,<br />

May 2002, pp.1-55, www.altera.com<br />

[10] “Using <strong>PLL</strong>s in Stratix Devices”, Altera Application Note 200, v.1.0, February 2002, pp.1-70,<br />

www.altera.com<br />

[11] “Superior Jitter Management with DLLs”, Virtech Tech Topic VTT013 (v.1.2), January 21, 2003, pp.1-6,<br />

www.xilinx.com<br />

[12] “Nios Embedded Processor Development Board”, Altera Data Sheet, v.2.1, April 2002, pp.1-22,<br />

www.altera.com/nios<br />

[13] “Metastability in Altera Devices”, Altera Application Note 42, v.4.0, May 1999, pp.1-10,<br />

www.altera.com<br />

[14] A. Rukhin, J. Soto, J. Nechvatal, M. Smid, E. Barker, S. Leigh, M. Levenson, M. Vangel, D. Banks, A.<br />

Heckert, J. Dray, S. Vo, “A statistical test suite for random and pseudorandom number generators for<br />

cryptographic applications“, NIST Special Publication 800-22, May 15, 2001, pp.1-153,<br />

http://csrc.nist.gov/rng/<br />

[15] S. Kim, K. Umeno, and A. Hasegawa, “Corrections of the NIST Statistical Test Suite for Randomness”,<br />

Cryptology ePrint Archive, Report 2004/018, January 26, 2004, http://eprint.iacr.org/2004/018.pdf

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