SIMPLE PLL-BASED TRUE RANDOM NUMBER ... - KEMT FEI TUKE

3 Randomness extraction from the PLL-generated clock jitter
The basic principle behind our method is to extract the randomness from the jitter of the
clock signal synthesized in the embedded analog PLL. The jitter is detected by the sampling
of a reference (clock) signal using a rationally related (clock) signal synthesized in the onchip
analog PLL. The fundamental problem lies in the fact that the reference signal has to
be sampled near the edges influenced by the jitter. The basic structure of the random
bitstream generator is depicted in Figure 3.
CLK
CLJ
PLL D
CLK
Q
D
CLK
Q
q(nTCLK)
Decimator
(NKD)
x(nNTQ)
Figure 3: Basic structure of random bitstream generator using PLL-synthesized low-jitter clock signal
Because there is a probability that the first flip-flop could become metastable, the
second flip-flop is cascaded. In case the first flip-flop produces a metastable output, it can
resolve until its output is clocked by the second flip-flop. This flip-flops connection does
not assure that only stable signal is clocked, but the probability that the output qn ( T CLK ) will
get a valid state is much higher [13].
Let CLJ be an on-chip PLL-synthesized rectangular clock waveform with the frequency
FCLJ = FCLK KM/ KD
(2)
where CLK is a reference clock signal and parameters K M and KD
defined in (1) are
related to the PLL structure. Signal CLJ is sampled into the D flip-flop using a clock signal
with frequency F CLK . There are KD rising edges of CLK signal and 2K M edges (rising and
falling) of CLJ waveform during time period
TQ = KDTCLK = KMTCLJ (3)
It has been shown in [6] that if K M and KD
are relative primes, the set of samples create an
equidistant set of values with the distance step
TCLK TCLJ
d = GCD( 2 KM, KD) = GCD( 2 KM,
K D)
(4)
2KM 2KD
where GCD means Greatest Common Divisor. It has been shown that the worst-case
distance between the two closest edges of CLK and CLJ during the period T Q is given as
( )
If KM, K D and F CLJ are chosen so, that
σ > MAX ( ∆ T )
MAX ∆ T = d /2
(5)
jit
we can guarantee that during T Q the sampling edge of CLK will fall at least once into the
edge zone of CLJ (the edge zone means the time interval around the edge with a width
smaller than σ jit ). Therefore during the period T Q , D values of CLJ will be sampled into
the first D flip-flop and at least one of them will statistically depend on the random jitter, so
the output value of the second flip-flop will be nondeterministic. In [6] we used
delay elements to increase the probability of overlapping of and CLJ edge zones.
K
qnT ( CLK )
CLK
min
min
(6)