In the Name of God, the Compassionate, the Merciful

In the Name of God, the Compassionate, the Merciful
S. Mehdi Fakhraie, Associate Professor
Director, Silicon Intelligence and VLSI Signal Processing Laboratory
School of Electrical and Computer Engineering
University College of Engineering
University of Tehran
North Kargar Ave., Tehran 14395-515, IR Iran
Phone: (+98-21) 6111 4340 (Office)
FAX: (+98-21) 8877 8690
E-mail: fakhraie@ut.ac.ir
Webpage : http://ece.ut.ac.ir/silab/mfakhraie
I. Education
Ph.D. in Electrical and Computer Engineering from the University of Toronto, Toronto, Canada, June
1995.
Thesis: VLSI-Compatible Implementations of Artificial Neural Networks.
M.Sc. in Electrical Engineering-Electronics from the University of Tehran, Iran, Feb. 1989.
M.Sc. Thesis: Real-Time Solution of Nonlinear Programming Problems by Analog
Hardware and Neural Computers.
B.Sc. Thesis: Iterative Fourier-Domain Solution of the Radiation Equation for a 2-D
Microstrip Antenna.
II. Professional Experience
• Associate Professor: School of Electrical and Computer Engineering, University of Tehran.
Taught graduate courses in advanced VLSI design, Custom Implementation of DSP Systems, and
Parallel Processing. Courses taught include undergraduate Digital Electronics, and VLSI System
Design. July 2004-present.
• Vice President in Research and Planning: National Elites Foundation, Tehran, Iran, from July
2007-Jan. 2010.
• Associate Dean for Research: University College of Engineering, University of Tehran, from
Sep. 2006-Sep. 2007.
• Associate Chair for Graduate Studies: School of Electrical and Computer Engineering,
University of Tehran, from Sep. 2004-Aug. 2006.
• Director of Silicon Intelligence and VLSI Signal Processing Laboratory, the University of
Tehran: Most-recent research included: Design and SoC/SoPC implementation of accelerating
engines for execution of genetic, fuzzy, and neural algorithms, bit-true modeling and VLSI
design of the DSP and MAC parts of wireless communication protocols including WiMAX
(802.16), VoIP over WiFi (802.11), UWB, DAB, and Zigbee, and low-power and high-speed
novel logic styles. Sep. 2004- present.
• Chairman of the Board, SiNA (Silicon in Networking Applications) Semiconductor Inc.,
Technology Park of the University of Tehran, Tehran, Iran: Developed algorithms and

•
designed ASIC and FPGA microchips and system boards for implementation of integrated
broadband gateways for secure office and home applications. Sep. 2004-present.
Executive Chair, the First, Second, and Third National Congresses of the Elites,
Tehran, Iran, August 2007, August 2008, and Oct. 2009.
• Executive Chair, the Second National Innovations and Inventions Festival, Tehran,
Iran, Feb. 2010.
• Executive Chair, the First, and Second International Conferences on Automotive
Electronics, Tehran, Iran, Feb. 2008 and Feb. 2009.
• Director, ASIC/SOC Design, Valence Semiconductor Inc., Toronto, Canada: Technical
supervision of a team of system and ASIC design engineers working on signal integrity and
power-grid analysis of Valence HomePlug six million transistor chip, and responsible for
Valence Family Radio System (FRS) baseband 2.5 million transistor chip in TSMC 0.25um
CMOS, a full-digital architecture with DSP-system power, speed and area optimization and
integrated GPS data link, and in charge of its physical implementation including layout
delivery and manufacturability tests. November 2002-April 2003.
• Director, VLSI Design of Valence Integrated Gateway Architecture, Valence
•
Semiconductor Inc., Dubai and Canada Offices: Developed architecture and implemented a
dual ARM946-8888, 20-block memory, 20-millioin transistor ASIC for a flexible yet
affordable voice-data gateway in TSMC 0.18um CMOS. January 2001-October 2002.
Consultant, Valence Semiconductor Inc.: Dubai and Canada Offices, Aug. 2000-Dec. 2000.
• Founding Director of VLSI Circuits and Systems Laboratory, the University of
Tehran: Most-recent research included: Design and implementation of dedicated DSP
hardware for digital subscriber lines (ADSL line-communication devices), and mobilecommunication
applications; design of customized high-performance architectures for parallel
DSP processors; development of several CMOS low-power logic styles; implementation of
analog artificial neural networks using submicron CMOS technologies; design of new efficient
architectures for FPGAs and FPGA applications in industrial environments; networks of
parallel processors and their applications. September 1996- June 2001.
• Executive Chair, the Twelfth IEEE International Conference on Mocroelectronics
(ICM 2000), Tehran, Iran, Oct. 30- Nov. 2, 2000, Conference Proceedings available on IEEE
Xplore site: http://ieeexplore.ieee.org .
• Associate Chair of Graduate Studies: Department of Electrical and Computer Engineering,
University of Tehran. September 1999-March 2000
• Director of Electronics Group: Department of Electrical and Computer Engineering,
University of Tehran, since Sep. 1996-March 2000.
• Assistant Professor: Department of Electrical and Computer Engineering, University of
Tehran. Taught graduate courses in advanced VLSI design, VLSI array processing, hardware
implementation of neural networks and intelligent systems, BiCMOS circuit design, and RF
Microelectronics. Courses taught include undergraduate Electronic Circuits, Digital
Electronics, Computer-Aided Design of Digital Circuits, and VLSI System Design. September
1995-July 2004.
• Research Assistant: Optoelectronics Lab, University of Toronto. Sept. 1993-Aug. 1995.
• Research Assistant: Computer Integrated Manufacturing and VLSI Research Laboratories,
University of Toronto. March 1991-August 1993.
• Teaching Assistant: Department of ECE, University of Toronto, sessions 1991/1992,
1992/1993, 1993/1994, 1994/1995.

• Instructor: Department of ECE, University of Tehran. Feb. 1989-Dec. 1990.
• Project Manager: Electronics Research Centre, University of Tehran. Feb. 1987-Aug. 1989.
• Electrical Engineer: Electronics Research Centre, University of Tehran. Jan. 1986-Jan. 1987.
• Researcher: Electronics Research Centre, University of Tehran. Aug. 1984-Dec. 1986.
III. Special Skills
• Architecture design of Network Processors and ASIC implementation of dedicated hardware for
high-speed manipulation of networking protocols: (Achievement: Valence Gateway processor,
emerged into IBG 20 million transistor product, 2001).
• Design with focus on extreme cost-performance efficiency of voice/data multi-protocol
integrated home/office gateways (Achievement: Valence Integrated Broadband Gateway (IBG)
product, 20 million transistors, 2002).
• Design and optimization of dedicated hardware for high-performance signal processing systems
(Achievements: Baseband 2.5 million transistor chip of Valence FRS system (2003), UT-VLSI
Lab Industrial Project: multi-protocol Flex/ERMES/POCSAG Pager chip (1999), and VLSI
Lab ADSL baseband processors (2000)).
• Design and implementation of general-purpose DSP hardware for mobile communication
applications (Achievements: VLSI Lab variants of DSP processors (1996-1999)).
• Integration and implementation of image processing systems (Privately-funded activity: FPGA
implementation of PCI high-speed image acquisition and processing system for midical and
dental imaging purposes (1999)).
• Development of wireless communication systems for sensor fusion, monitoring and control
(VLSI Lab Industrial Project: Custom wireless communication system, FPGA-MCU ASIC
preparation of baseband system and fabricated bipolar integrated front end (1997-1999)) .
• Design of dedicated hardware for one-way and two-way paging systems (Prepared working
design on 8051 MCU/FPGA based platform for ASIC development environment (1998)).
• Application of DSP systems to industrial environments (UT-VLSI Lab study based on developed
ASIC designs (1997)).
• Industrial applications of Artificial Neural Networks (University of Toronto summer studies
(1997-2000)).
• Simulation, design, hardware implementation, and after-fabrication programming and test of
custom-designed neural-network hardware (University of Toronto(1994-1995)).
• Design and implementation of mixed analog-digital circuits (employing memories, buffers,
multiplexers, and dedicated analog processing engines for intelligent systems (1993-1995).
• Certificate of Synopsys Inc. for VHDL synthesis and simulation training courses (1994).
• Full familiarity with Cadence integrated design environment including NCSim Verification,
BuildGtes Extreme Synthesis and Power Optimization, SOC Encounter, Celtic crosstalk
analysis, and Voltage Storm power grid analysis tools (used in making many digital and analog
IC chips).
• Set up of the environment and teaching of VLSI design using MAGIC and LEDIT VLSI design
tools.
• Design, installation, programming, and maintenance of computer-controlled IC test systems.
• Programming experience with C and C++ languages: writing system-level and behavioral
simulators for pre-implementation studies. Extensive experience with MATLAB and its signalprocessing
and neural-network toolboxes.
• Familiarity with different PC-based and UNIX-based computational platforms.
• Design and programming of various analog and digital data acquisition systems.

• Working and programming of HP and Keithley semiconductor analysis instruments.
• Parallel programming and applications of parallel array processors.
• Integration and optimization of digital systems using integrated circuits technology.
IV. Research Interests: Present and Future
• Intelligent Processor Convergence: I have had plenty of activities on design of generalpurpose
processors, DSP customized hardware engines, cores for intelligent systems, and
network processors. In addition, I have designed and implemented several generations of
mixed-mode neural network intelligent processing systems. Now, I wish to work on the
idea of “Intelligent Processor Convergence,” in the context of the massive market for
intelligent signal-processing and home/office networking products, a context that adopts
the best of all worlds for highest cost/performnace to supply such pieces of hardware to
improve the life of every human being.
• Network processor and broadband gateway architectures and their implementation:
I have worked as director of an industrial team working on development of dedicated
hardware and related software for highly integrated, high-speed, and yet-affordable
home gateway processors. I realize that there are many improvements and optimizations
in architecture and implementation of gateway chips that would allow them to become
an affordable integral part of every home in the world.
• Fully-optimized low-power DSP engines for communication systems: My previous
experience includes development of custom engines for low-power FRS baseband chip;
two-way and one-way multi-protocol paging systems; and a custom ADSL system.
These activities have led me to identify many improvements in DSP algorithms and
their implementation which potentially open up new horizons for reducing area, power
and system-integration costs while improving the performance.
• Manufacturability and Signal Integrity of ASIC chips: Having worked on the power
grid analysis and signal integrity of the Valence six million transistor Home Plug ASIC
chip, I have been in short of tools and methodologies to incorporate SI and power
related timing considerations in the design cycle right from beginning of RTL synthesis
and chip planning. Database convergence, virtual chip prototyping, concept of wire
synthesis, realistic interconnect delay estimation, extra delay margins considered from
the beginning, and rapid detail routing are all techniques that are partly investigated by
Cadence and Synopsys, but none has been evolved into a mature design flow, and there
are yet many flaws to fill.
• VLSI implementation of general DSP processors for communication applications:
Having directed a 15-member team working in collaboration with industry on design and
VLSI implementation of a dedicated DSP processor for use in GSM mobile handsets, I
am in a position to clearly recognize that the future mobile systems will constitute of a
mixture of general processors and custom coprocessing hardware. This is a fact
recognized by other researchers as well yielding to development of configurableinstruction
processors and their required CAD tools. However, packetized-data mobile
systems are in need of efficient packet processors as well. This is an area that I feel I am
in a good position to contribute. I have worked on and have suggestions for many
variants of such processors to be developed.
• Development of hardware-emulation systems and custom ASIC development boards:
Hardware and software have been developed at UT-VLSI lab and several ASIC
development industrial projects to provide high-performance FPGA systems for rapid
evaluation of complex digital systems with maximum capacity of 30 million equivalent
gates. Several generations of these projects have been constructed. The one with
100,000 equivalent-gate capacity has been used for DSP processor development
emulation. Another embedded system with 8051 CPU, memory, and FPGA was

developed and used in a two-way messaging (pager) project. Nowadays, embedded
system IP providers development systems (e.g. MIPS nad ARM) will make average
users needless of custom developments. However, an active development team should
come with the expertise and speed to assemble custom development environments.
Such a need appears almost always at interfaces side even when using some existing
development systems, as we have done with ARM Integrated System and our custom
interfaces in Valence Semiconductor Inc. and with our custom development
environment for integrated broadband gateway ASIC at SiNA Semiconductor Inc.
• Hardware implementation of artificial neural networks (ANNs): Through theoretical
analysis, extensive simulations using our custom-designed neural network simulator written in
C, HSPICE circuit simulations, development of a new device and its model, and several cycles
of chip fabrication, we have designed a new class of efficiently-hardware-implementable
ANNs that employ a single MOS transistor as their synaptic block. The whole idea has been
verified by a 10,000-transistor final test chip including 15 neurons and 270 synapses connected
in three layers. Development of denser and more integrated digitally-interfaced analog-anddigital
processing intelligent systems and neural networks are things that I see as future mustto-do
activities.
• Mixed-mode implementation of ANNs in submicron CMOS technologies: Developed,
fabricated, and tested a 0.35um analog neural network with 3-D closed-boundary
discriminating surfaces for pattern classification and recognition applications. This
research has brought new ideas towards integration and application of mixed mode
analog-digital massively parallel integrated systems with potential applications in
intelligent systems and man-machine interface as outlined above.

V. Publications
Books
[1] S. Mehdi Fakhraie and K.C. Smith, VLSI-Compatible Implementations for Artificial
Neural Networks. Boston: Kluwer Academic Publishers, 1997.
Papers
Journal Papers
[1] F. Firouzi, M. E. Salehi, F. Wang, and S. M. Fakhraie, “An accurate model for soft error
rate estimation considering dynamic voltage and frequency scaling effects,” in Elsevier
Microelectronics Reliability, accepted for publication,
doi:10.1016/j.microrel.2010.08.016.
[2] Mostafa E. Salehi, Mehrzad Samadi, Mehrdad Najibi, Ali Afzali-Kusha, Masoud Pedram,
and Sied Mehdi Fakhraie, “Dynamic voltage and frequency scheduling for embedded
processors considering power/performance tradeoffs,” in IEEE Transactions on Very
Large Scale Integration (VLSI) Systems, accepted for publication, Digital Object
Identifier: 10.1109/TVLSI.2010.2057520.
[3] H. Parandeh-Afshar, S. M. Fakhraie, and O. Fatemi, “Parallel merged multiplieraccumulator
coprocessor optimized for digital filters,” in Elsevier Journal of Computers
& Electrical Engineering, vol. 36, issue 5, pp. 864-873, Sep. 2010.
[4] H. R. Mahdiani, A. Ahmadi, S. M. Fakhraie, and C. Lucas, “Bio-inspired imprecise
computational blocks for efficient VLSI implementation of Soft-Computing Applications,”
in IEEE Trans. Circuits and Systems I: Regular papers, pp. 850-862, vol. 57, no. 4,
April 2010.
[5] Amin Farmahini-Farahani, Shervin Vakili, Sied Mehdi Fakhraie, Saeed Safari, and Caro
Lucas, “Parallel scalable hardware implementation of asynchronous discrete particle swarm
optimization,” in Elsevier Journal of Engineering Applications of Artificial
Intelligence, vol. 23, no. 2, pp. 177-187, March 2010.
[6] S. Vakili, S. M. Fakhraie, and S. Mohammadi, “Evolvable multi-processor: a novel MPSoC
architecture with evolvable task decomposition and scheduling,” in IET Comput. Digit.
Tech., vol. 4, no. 2, pp. 143–156, March 2010.
[7] Mostafa E. Salehi and Sied Mehdi Fakhraie, “Quantitative analysis of packet-processing
applications regarding architectural guidelines for network-processing-engine
development,” in Elsevier Journal of System Architecture, vol. 55, no. 7-9, pp. 373–
386, Sep. 2009.
[8] H. R. Mahdiani and S. M. Fakhraie, “A cost-error tunable round-off method: Finite-length
absorption,” IEICE Electronic Express, vol. 6, no. 18, pp. 1312-1317, Sep. 2009.
[9] S. Vakili, S. M. Fakhraie, S. Mohammadi, and A. Ahmadi, “Low-cost fault tolerance in
evolvable multiprocessor systems: A graceful degradation approach,” Journal of Zhejiang
University-Science A, co-published with Springer-Verlag GmbH, vol. 10, no. 6, pp.
922-926, June 2009.
[10] M. Hamzeh, H. R. Mahdiani, A. Saghafi, S. M. Fakhraie, and C. Lucas, “Computationally
efficient active rule detection method: Algorithm and architecture,” in Elsevier Fuzzy Sets
and Systems, vol. 160, no. 4, pp. 554-568, Feb. 2009.
[11] F. Kashfi, S. M. Fakhraie, and S. Safari, “Designing an ultra-high-speed multiply-accumulate
structure,” in Elsevier Microelectronics Journal, vol. 39, no. 12, pp. 1476-1484, Dec.
2008.

[12] S. Rahmanian and S. Mehdi Fakhraie, “An optimal structure for implementation of digital
filters,” in IEICE Electronic Express, vol. 4, no. 21, pp. 679-683, Nov. 2007.
[13] F. Kashfi, A. Agah, S. Mehdi Fakhraie, and S. Safari, “15 GHz low-voltage-swing carrylookahead
adder,” in IEICE Electronic Express, vol. 4, no. 22, pp. 696-700, Nov. 2007.
[14] Mahdi Hamzeh, Sied Mehdi Fakhraie, and Caro Lucas, "Soft real-time fuzzy task
scheduling for multiprocessor systems," in International Journal of Intelligent
Technology, vol. 2, no. 4, pp. 211-216, Sep. 2007.
[15] R. Rafati, S. Mehdi Fakhraie, and K. C. Smith, "A 16-bit barrel-shifter implemented in
data-driven dynamic logic," in IEEE Trans. Circuits and Systems I: Regular papers, pp.
2194-2202, vol. 53, no. 10, Oct. 2006.
[16] S. Rahimian Omam, S. M. Fakhraie, and O. Shoaei, “Minimizing the adder cost in multiple
constant multipliers,” in IEICE Electronic Express, vol. 3, no. 14, pp. 340-346, July 2006.
[17] A. Pedram, M. R. Jamali, T. Pedram, S. M. Fakhraie, and C. Lucas, “Local linear model
tree (LOLIMOT) reconfigurable parallel hardware,” in Transactions on Engineering,
Computing and Technology, Poland, vol. 13, pp. 96-101, May 2006.
[18] E. Rohani and S. Mehdi Fakhraie, "Round-off error in block floating point structures," in
IEE Electronics Letters, vol. 42, no. 3, Feb. 2006.
[19] R. Rafati and S. Mehdi Fakhraie, "Data-driven dynamic logic," in Journal of the Faculty
of Engineering of the University of Tehran, Fall 2005, (in Farsi).
[20] S. Shamshiri, S. M. Fakhraie, and C. Lucas, "A genetic-algorithm solution for designing
optimal forwarding tables," in Nasir J. of Science and Engineering, vol. 1, no. 1, Summer
2005, (in Farsi).
[21] S. Shamshiri and S. M. Fakhraie, "Genetic algorithm memory minimization for designing
reconfigurable address lookup engine," in Int. J. of Computational Intelligence and
Applications, Imperial College Press, vol. 5, no. 1, pp. 69-80, March 2005.
[22] S. R. Abdollahi, S. M. Fakhraie, and M. Kamarei, "A crystal-based low-voltage all-digital
programmable ring oscillator," in Analog Integrated Circuits and Signal Processing,
Springer Science (Formerly published by Kluwer Academic Publishers), vol. 43, no. 2,
pp. 147 – 157, May 2005.
[23] Mehran Nadjarbashi, S. Mehdi Fakhraie, and Alireza Kaviani, “On routing architecture for
hybrid FPGA,” in Int. J. of Science and Technology: Scientia Iranica, vol. 11, no. 3, pp.
159-164, Summer 2004.
[24] S. M. Fakhraie, H. Farshbaf, and K.C. Smith, "Scalable closed-boundary analog neural
networks," in IEEE Trans. Neural Networks, vol. 15, no. 2, pp. 492-504, March 2004.
[25] M. H. Tehranipour, S. M. Fakhraie, M. R. Movahedin, and Z. Navabi, "A low-cost at-speed
BIST architecture for embedded processor and SRAM cores," in Journal of Electronic
Testing, Theory and Applications, Kluwer Academic Publishers, vol. 20, pp. 155-168,
April 2004.
[26] M. H. Tehranipour, S. M. Fakhraie, M. Nourani, Z. Navabi, and M. R. Movahedin,
"Embedded test for processor and memory cores in system-on-chips," in Int. J. of Science
and Technology: Scientia Iranica, vol. 10, no. 4, pp. 486-494, Oct. 2003.
[27] H. Zarei, O. Shoaei, and S. M. Fakhraie, “A 37-mW fully integrated GMSK modulator for
DRRS standard in 0.6-um digital CMOS process,” in IEEE Trans. Circuits and Systems
II, vol. 49, no. 7, pp. 513-520, July 2002.
[28] B. S. Biria, S. M. Fakhraie, and C. Lucas, “Improvement of neural networks generalization
by adaptive regularization parameters,” in Amirkabir Journal of Science and
Technology, vol. 11, no. 43, pp. 348-360, Spring 2000, (in Farsi).

[29] A. Shamaie, S. M. Fakhraie, and B. Benhabib, “A new technique for accurate estimation of
partly-occluded-ellipse parameters,” in Int. J. of Science and Technology: Scientia
Iranica, Electrical Engineering Issue, Fall 1999.
[30] S. Mehdi Fakhraie, A. Konrad, and K.C. Smith, “Neuro-computation techniques in
sampled-data electromagnetic-field problems,” in IEEE Trans. Magnetics, vol. 30, no. 5,
pp. 3637-3640, Sep.1994.

Reviewed Conference Papers (Published in Proceedings of International Conferences):
[31] A. Yazdanbakhsh, M. E. Salehi, S. Safari, and S. M. Fakhraie, “Locality considerations in
exploring custom instruction selection algorithms,” in Proc. 2nd Asia Symposium on
Quality Electronic Design (ASQED2010), Penang, Malaysia, pp. 157-162, Aug. 2010.
[32] F. Firouzi, S. Kiamehr, P. Monshizadeh, M. Saremi, A. Afzali-Kusha, and S. M. Fakhraie,
“A model for transient fault propagation considering glitch amplitude and rise-fall time
mismatch,” in Proc. 2nd Asia Symposium on Quality Electronic Design (ASQED2010),
Penang, Malaysia, pp. 89-92, Aug. 2010.
[33] S. R. Abdollahi, H. S. Al-Raweshidy, S. Mehdi Fakhraie,R. Nilavalan, and M. Kamarei,
“Full duplex 60 GHz millimeter wave transmission over multi-mode fiber,” in Proc. Second
International Conference on Ubiquitous and Future Networks (ICUFN 2010), Jejo
Island, Korea, pp. 222-226, June 2010.
[34] M. Ahmadi and S. M. Fakhraie, “Optimization of Viterbi decoder parameters for WRAN
system,” in Proc. 2nd International Conference on Future Computer and
Communication (ICFCC), 2010, Wuhan, China, pp. V3-53-56, May 2010.
[35] M. Ahmadi, E. Rohani, Pooya Monshizadeh Naeeni, and S. M. Fakhraie, “Modeling and
performance evaluation of IEEE 802.22 physical layer,” in Proc. 2nd International
Conference on Future Computer and Communication (ICFCC), 2010, Wuhan, China,
pp. V3-62-66, May 2010.
[36] A. Azarpeyvand, M. E. Salehi, F. Firouzi, A. Yazdanbakhsh, and S. M. Fakhraie, “Instruction
reliability analysis for embedded processors,” in Proc. IEEE 13th International
Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS),
2010, Vienna, Austria, pp. 23-26, April 2010.
[37] A. Rahimi, M. E. Salehi, S. Mohammadi, S. M. Fakhraie, A. Azarpeyvand,
“Energy/throughput trade-off in a fully asynchronous NoC for GALS-based MPSoC
architectures,” in Proc. 5th International Conference on Design and Technology of
Integrated Systems in Nanoscale Era (DTIS), 2010, Hammamet, Tunisia, pp. 1-6, March
2010.
[38] F. Firouzi, M. Salehi, A. Azarpeyvand, S. M. Fakhraie, and F. Wang, “Reliability
considerations in dynamic voltage and frequency scaling schemes,” in Proc. 5th
International Conference on Design and Technology of Integrated Systems in Nanoscale
Era (DTIS), 2010, Hammamet, Tunisia, pp. 1-4, March 2010.
[39] A. Yazdanbakhsh, M. E. Salehi, and S. M. Fakhraie, “Architecture-aware graph-covering
algorithm for custom instruction selection,” in Proc. 5th International Conference on
Future Information Technology (FutureTech), 2010, Busan, Korea, pp. 1-6, May 2010.
[40] P. M. Naini, S. M. Fakhraie, and A. N. Avanaki, “Sudoku Bit Arrangement for Combined
Demosaicking and Watermarking in Digital Camera,” in Proc. Second International
Conference on Advances in Databases Knowledge and Data Applications (DBKDA),
2010, Menuires, France, pp. 41-44, April 2010.
[41] Z. Sharifi Mehrjardi, N. Kazemian Amiri, and S. M. Fakhraie, “Bit-width optimization of
CS-ACELP speech coder by SIMULINK: Core layer of the new G.729.1 standard,” in Proc.
14th International CSI Computer Conference, 2009, (CSICC 2009), pp. 507-511, 20-21
Oct. 2009.

[42] P. Monshizadeh Naeeni, A. Nasiri Avanaki, and S. M. Fakhraie, “A new approach for
combined demosaicking and watermarking in digital camera pipeline,” in Proc. Fifth
International Joint Conference on INC, IMS and IDC, 2009, (NCM '09), pp. 1246-1250,
25-27 Aug. 2009.
[43] S. Vakili, S. M. Fakhraie, S. Mohammadi, and A. Ahmadi, “Particle swarm optimization
for run-ime task decomposition and scheduling in evolvable MPSoC,” in Proc.
International Conference on Computer Engineering and Technology 2009, vol. 2, pp.
28-32, 22-24 Jan. 2009.
[44] R. Yousefi, A. Jalili, and S. M. Fakhraie, “Frequency domain testing: A new approach in
online test of VLSI digital signal processing systems,” in Proc. International Conference
on Computer Engineering and Technology 2009, vol. 2, pp. 136-140, 22-24 Jan. 2009.
[45] A. Jalili, R. Yousefi, S. M. Fakhraie, and S. Nader-Esfahani, “Effects of different mobile
channel conditions on IEEE 802.20,” in Proc. International Conference on Computer
Engineering and Technology 2009, vol. 2, pp. 287-291, 22-24 Jan. 2009.
[46] A. Ahmadi, S. M. Fakhraie, and C. Lucas, “Behavioral fault model for neural networks,” in
Proc. International Conference on Computer Engineering and Technology 2009, vol. 2,
pp. 71-75, 22-24 Jan. 2009.
[47] A. Ahmadi, M. H. Sargolzaie, S. M. Fakhraie, C. Lucas, and S. Vakili, “A low-cost faulttolerant
approach for hardware implementation of artificial neural networks,” in Proc.
International Conference on Computer Engineering and Technology 2009, vol. 2, pp.
93-97, 22-24 Jan. 2009.
[48] A. Jalili, S. M. Fakhraie, and S. Nader-Esfahani, “Performance evaluation of IEEE 802.20
PHY layer,” in Proc. International Conference on Computer Engineering and
Technology 2009, vol. 2, pp. 161-165, 22-24 Jan. 2009.
[49] F. Kashfi,S. M. Fakhraie, and S. Safari, “A 65nm 10GHz pipelined MAC structure,” in
Proc. IEEE International Symposium on Circuits and Systems, 2008, (ISCAS 2008), pp.
460-463, 18-21 May 2008.
[50] R. Yousefi, M. H. Sargolzaie, and S. M. Fakhraie, “Low cost concurrent error detection for
lattice wave digital filters,” in Proc. International Symposium onTelecommunications,
2008, (IST 2008), pp. 598-601, 27-28 Aug. 2008.
[51] E. Rohani and S. M. Fakhraie, “Optimum design of Viterbi decoder for high speed data
telecommunication receivers with 802.16a case study,” in Proc. International Symposium
onTelecommunications, 2008, (IST 2008), pp. 246-250, 27-28 Aug. 2008.
[52] Z. Pajouhi, S. M. Fakhraie, and S. H. Jamali, “Hardware implementation of a 802.11n
MIMO OFDM transceiver,” in Proc. International Symposium onTelecommunications,
2008, (IST 2008), pp. 414-419, 27-28 Aug. 2008.
[53] R. Yousefi, A. Ahmadi, and S. M. Fakhraie, “Design flow for hardware implementation of
digital filters,” in Proc. International Symposium onTelecommunications, 2008, (IST
2008), pp. 586-591, 27-28 Aug. 2008.
[54] A. Farmahini-Farahani, S. M. Fakhraie, and S. Safari, “Scalable architecture for on-chip
neural network training using swarm intelligence,” in Proc. Design, Automation and Test
in Europe, 2008, (DATE '08), pp. 1340-1345, 10-14 March 2008.
[55] R. Yousefi, M. H. Sargolzaie, and S. M. Fakhraie, “Online and offline test unification in
digital filters,” in Proc. International Conference on Innovations in Information
Technology, 2008, (IIT 2008), pp. 111-115, 16-18 Dec. 2008.

[56] R. Yousefi and S. M. Fakhraie, “Frequency domain concurrent error detection in DSP
systems,” in Proc. International Conference on Innovations in Information Technology,
2008, (IIT 2008), pp. 54-58, 16-18 Dec. 2008.
[57] S. Vakili, S. M. Fakhraie, and S. Mohammadi, “Designing an MPSoC architecture with runtime
and evolvable task decomposition and scheduling: A neural network case study,” in
Proc. International Conference on Innovations in Information Technology, 2008, (IIT
2008), pp. 106-110, 16-18 Dec. 2008.
[58] M. Hamzeh, S. Arab, S. M. Fakhraie, and C. Lucas, “An improvement on LEACH
algorithm with a fuzzy processor,” in Proc. 14th Asia-Pacific Conference on
Communications, 2008, (APCC 2008), pp. 1-5, 14-16 Oct. 2008.
[59] N. Sedaghati-Mokhtari, M. Nazm-Bojnordi, A. Hormati, and S. M. Fakhraie, “An efficient
and extendable modeling approach for VLIW DSP processors,” in Proc. 13th International
Computer Society of Iran Computer Conference, March 9-11, 2008, Kish Isl., Iran,
published by Springer-Verlag Berlin, Advances in Computer Science and Engineering,
vol. 6, pp. 267-274, 2008.
[60] Mostafa E. Salehi, S. M. Fakhraie, A. Banaiyan, and A. Hormati, “Design of a custom
packet switching engine for network applications,” in Proc. 13th International Computer
Society of Iran Computer Conference, March 9-11, 2008, Kish Isl., Iran, published by
Springer-Verlag Berlin, Advances in Computer Science and Engineering, vol. 6, pp.
786–790, 2008.
[61] N. Kazemian Amiri, S. M. Fakhraie,G. A. Hosein-Zadeh, and S. M. Mousavinejad,
“Modeling of ITU-T G.729 codec with bit-width optimization for intensive computation
blocks,” in Proc. Internatonal Conference on Microelectronics, 2007, (ICM 2007), pp.
47-50, 29-31 Dec. 2007.
[62] S. A. Sadrossadat, N. Kazemian Amiri, and S. M. Fakhraie, “An efficient multi-operand
addition structure,” in Proc. Internatonal Conference on Microelectronics, 2007, (ICM
2007), pp. 73-76, 29-31 Dec. 2007.
[63] B. Zamanlooy, A. Ayatollahi, S. M. Fakhraie, M. Chahardori, “Investigating different circuit
styles for digital circuits using organic transistors,” in Proc. International Symposium on
Integrated Circuits, 2007, (ISIC '07), pp. 5-8, 26-28 Sept. 2007.
[64] A. Saghafi and S. M. Fakhraie, “An exact analysis of the linear serial acquisition for ultrawideband
communication systems,” in Proc. IEEE International Conference on Ultra-
Wideband, 2007, (ICUWB 2007), Singapore, pp. 880-883, 24-26 Sep. 2007.
[65] A. Saghafi and S. M. Fakhraie, “Optimized baseband design of an ultra-wideband impulse
radio receiver,” in Proc. IEEE International Conference on Ultra-Wideband, 2007,
(ICUWB 2007), Singapore, pp. 805-808, 24-26 Sep. 2007.
[66] A. Farmahini-Farahani, S. M. Fakhraie, and S. Safari, “SOPC-based architecture for discrete
particle swarm optimization,” in Proc. 14 th IEEE International Conference on
Electronics, Circuits and Systems, 2007, (ICECS 2007), Marrakech, Morocco, pp. 1003-
1006, 11-14 Dec. 2007.
[67] N. Sedaghati-Mokhtari, M. N. Bojnordi, A. Farmahini-Farahani, M. Mousavinezhad, and S.
M. Fakhraie, “Simulation of voice processing applications through VLIW DSP
architectures,” in Proc. 14 th IEEE International Conference on Electronics, Circuits and
Systems, 2007, (ICECS 2007), Marrakech, Morocco, pp. 291-293, 11-14 Dec. 2007.

[68] N. Sedaghati-Mokhtari, M. N. Bojnordi, and S. M. Fakhraie, “MDST: Multiprocessor DSP
simulation toolkit for voice processing applications,” in Proc. 15 th International
Symposium on Modeling, Analysis, and Simulation of Computer and
Telecommunication Systems, 2007, (MASCOTS '07), Istanbul, Turkey, pp. 173-178, 24-26
Oct. 2007.
[69] A. Farmahini-Farahani, M. Laali, A. Moghimi, and S. M. Fakhraie, S. Safari, “Mesh
architecture for hardware implementation of particle swarm optimization,” in Proc.
International Conference on Intelligent and Advanced Systems, 2007, (ICIAS 2007),
Kuala Lumpur, Malaysia, pp. 1300-1305, 25-28 Nov. 2007.
[70] S. M. Mortazavi Zanjani, S. Rahimian Omam, S. M. Fakhraie, and O. Shoaei,
“Experimental evaluation of different realizations of recursive CIC filters,” in Proc.
Canadian Conference on Electrical and Computer Engineering, 2006, (CCECE '06),
Ottawa, Canada, pp. 1056-1059, May 2006.
[71] S. M. Mortazavi Zanjani, S. Rahimian Omam, S. M. Fakhraie, and O. Shoaei, “Algorithmic
design of high-precision low-power multi-stage decimation filters,” in Proc. 49th IEEE
International Midwest Symposium on Circuits and Systems, 2006, (MWSCAS '06), vol.
2, pp. 184-187, 6-9 Aug. 2006.
[72] Somayyeh Rahimian Omam, S. M. Mortazavi Zanjani, S. M. Fakhraie, and O. Shoaei,
“Design of high-precision low-power interpolation modules with modified SINC filters,” in
Proc. 49th IEEE International Midwest Symposium on Circuits and Systems, 2006,
(MWSCAS '06), vol. 1, pp. 620-624, 6-9 Aug. 2006.
[73] Ardavan Pedram, Masoud Daneshtalab, and Sied Mehdi Fakhraie “An efficient parallel
architecture for matrix computations,” in Proc. 24 th Norchip Conference, pp. 171-174, Nov.
2006.
[74] Somayyeh Rahimian Omam, S. M. Mortazavi Zanjani, S. M. Fakhraie, and O. Shoaei,
“Implementation of multiplier block with reduced adder cost,” in Proc. 13 th IEEE
International Conference on Electronics, Circuits and Systems, 2006, (ICECS 2006), pp.
842-845, 10-13 Dec. 2006.
[75] S. M. Mortazavi Zanjani, S. M. Fakhraie, O. Shoaei, and M. E. Salehi, “Design of FIR
filters using identical subfilters of even length,” in Proc. International Conference on
Microelectronics, 2006, (ICM '06), pp. 83-86, 16-19 Dec. 2006.
[76] M. Najibi, M. Salehi, A. A. Kusha, M. Pedram, S. M. Fakhraie, and H. Pedram, “Dynamic
voltage and frequency management based on variable update intervals for frequency setting,”
in Proc. IEEE/ACM International Conference on Computer-Aided Design, 2006,
(ICCAD '06), pp. 755-760, 5-9 Nov. 2006.
[77] H. Esmaeilzadeh, M. R. Jamali, P. Saeedi, A. Moghimi, C. Lucas, S. M. Fakhraie, "NNEP,
design pattern for neural-network-based embedded systems," in 14 th Int. Conf. Mixed
Design 2007 (MIXDES 2007), Poland, pp. 673-678, June 2007.
[78] Amir Agah, S. Mehdi Fakhraie, and A. Emami-Neyestanak, "Tertiary-Tree 12-GHz 32-bit
Adder in 65nm Technology," in Proc. IEEE Int. Symposium Circuits and Systems
(ISCAS07), New Orleans, USA, pp. 3006-3009, May 2007.
[79] Ahmad Saghafi and S. Mehdi Fakhraie, "A new search space reduction technique for
acquisition of UWB signals in multipath channels," in IEEE 65th Vehicular Technology
Conference (VTC2007-Spring), Dublin, Ireland, pp. 1559-1563, April 2007.

[80] A. Farmahini-Farahani, M. Kamal, S. M. Fakhraie, and S. Safari, “HW/SW partitioning
using discrete particle swarm,” in Proc. Great Lakes Symposium on VLSI, Stresa-Lago
Maggiore, Italy, pp. 359-364, Mar. 11-13, 2007.
[81] N. Kazemian Amiri and S. M. Fakhraie, “Digital network echo cancellation using genetic
algorithm and combined GA-LMS method,” in Proc. Asian Pacific Conference on Circuits
and Systems (APCCAS’06), Singapore, pp. 1822-1825, Dec. 4-7, 2006.
[82] Z. Pajouhi and S. M. Fakhraie, ”A novel neural network GA-optimized controller for QoS
support in wireless MACs,” in Proc. Asian Pacific Conference on Circuits and Systems
(APCCAS’06), Singapore, pp. 1527-1530, Dec. 4-7, 2006.
[83] M. Nabipoor, S. A. Khodaian, N. Sedaghati-Mokhtari, S. M. Fakhraie, and S. H. Jamali, "A
high-speed low-complexity VLIS SISO architecture," in Proc. Asian Pacific Conference on
Circuits and Systems (APCCAS’06), pp. 1512-1515, Singapore, Dec. 4-7, 2006.
[84] A. Saghafi and S. M. Fakhraie, "Rapid Acquisition of Ultra-Wideband Signals in Multipath
Environments," in Proc. Asian Pacific Conference on Circuits and Systems
(APCCAS’06), pp. 1818-1821, Singapore, Dec. 4-7, 2006.
[85] N. Moezi-Madani, H. Holisaz, and S. M. Fakhraie, "Digital audio broadcasting system
modeling and hardware implementation," in Proc. Asian Pacific Conference on Circuits
and Systems (APCCAS’06), pp. 1814-1817, Singapore, Dec. 4-7, 2006.
[86] E. Rahmani, S. M. Fakhraie, and M. Kamarei, “Finding Agent-Based Energy-Efficient
Routing in Sensor Networks using Parallel Genetic Algorithm”, in Proc. Int. Conf.
Microelectronics 2006 (ICM06), Saudi Arabia, pp. 119-122, Dec. 16-19, 2006.
[87] S. Rahmanian, E. Rahmani, A. Nasiri, and S. M. Fakhraie, “An Optimal Structure for
Implementation of Digital Filters,” in Proc. Int. Conf. Microelectronics 2006 (ICM06),
Saudi Arabia, pp. 95-98, Dec. 16-19, 2006.
[88] A. Pedram, M. Daneshtalab, N. Sedaghati-Mokhtari, and S. M. Fakhraie, “A highperformance
memory-efficient parallel hardware for matrix computation in signal processing
applications,” in Proc. Int. Symposium on Communication and Information Technology
(ISCIT06), pp. T2D-2-7, Bangkok, Thailand, Oct. 18-20, 2006.
[89] F. Montazeri, M. Salmani-Jelodar, S. N. Fakhraie, and S. M. Fakhraie, "Evolutionary
multiprocessor task scheduling," in Proc. PARELEC 2006, Poland, pp. 68-76, Sep. 2006.
[90] A. Pedram, M. R. Jamali, S. M. Fakhraie, and C. Lucas,"Reconfigurable parallel hardware
for computing local linear neuro-fuzzy model," in Proc. PARELEC 2006, Poland, pp. 198-
201, Sep. 2006.
[91] A. Banaiyan, H.R. Mahdiani, and S. M. Fakhraie, "Software implementation issues of
existing and new defuzzificztion methods," in Proc. 2006 IEEE World Congress
Computational Intelligence, Vancouver, Canada, pp. 8476-8481, July 2006.
[92] M. Salmani Jelodar, Najmeh Fakhraie, Faeze Montazeri, S. Mehdi Fakhraie, and M. Nili
Ahmadabadi, "A representation for genetic-algorithm-based multiprocessor task scheduling,"
Proc. 2006 IEEE World Congress Computational Intelligence, Vancouver, Canada, pp.
1044-1051, July 2006.
[93] M. Salmani Jelodar, Mehdi Kamal, S. Mehdi Fakhraie, and M. Nili Ahmadabadi, "SOPCbased
parallel genetic algorithm," in Proc. 2006 IEEE World Congress Computational
Intelligence, Vancouver, Canada, pp. 9705-9711, July 2006.
[94] A. Banaiyan, H. R. Mahdiani, and S. Mehdi Fakhraie, "PiFie: A platform-independent fuzzy
instruction set extension," in Proc. NAFIPS06, Montreal, Canada, June 2006.

[95] A. Banaiyan, M. Salmani Jelodar, and S. Mehdi Fakhraie, "ISA extension to general purpose
processors for fuzzy and genetic algorithm applications," in Proc. NAFIPS06, Montreal,
Canada, June 2006.
[96] H. Esmaeilzadeh, P. Saeedi, B. N. Araabi, C. Lucas, and S. M. Fakhraie, “Neural network
stream processing core (NnSP) for embedded systems,” in Proc. IEEE Int. Symposium
Circuits and Systems (ISCAS06), pp. 2773-2776, Greece, May 2006.
[97] H. Esmaeilzadeh, A. Moghimi, E. Ebrahimi, C. Lucas, Z. Navabi, and S. M. Fakhraie,
“DCim++: A C++ library for object oriented hardware design and distributed simulation,” in
Proc. IEEE Int. Symposium Circuits and Systems (ISCAS06), pp. 1283-1286, Greece,
May 2006.
[98] F. Kashfi and S. M. Fakhraie, “Implementation of a high-speed low-power 32-bit adder in
70nm technology,” in Proc. IEEE Int. Symposium Circuits and Systems (ISCAS06), pp.
9-12, Greece, May 2006.
[99] H. R. Mahdiani, A. Banaiyan, and S. M. Fakhraie, “Hardware implementation and
comparison of new defuzzification techniques in fuzzy processors,” in Proc. Symposium
Circuits and Systems (ISCAS06), pp. 4619-4622, Greece, May 2006.
[100] M. Salmani Jelodar, S. M. Fakhraie, and M. Nili Ahmadabadi, "Two-stage morphological
filter design using genetic algorithms," in Proc. IEEE Int. Conf. Engineering of Intelligent
Systems (ICEIS06), pp. 129-133, Islamabad, Pakistan, May 2006.
[101] H. Holisaz, S. Shamshiri, F. Baharvand, and S. Mehdi Fakhraie, "Hardware Accelerator IP
core for wireless 802.16 MAC," in Proc. Third Wireless and Optical Communication
Networks (WOCN), pp. 1-5, India, April 2006.
[102] H. Hollisaz, N. Moezzi Madani, and S. Mehdi Fakhraie, "A quantitative approach to digital
filter implementation," Proc. IEEE International Conference on Microelectronics 2005,
pp. 160-164, Pakistan, Dec. 2005.
[103] N. Moezzi-Madani, E. Rohani, and S. Mehdi Fakhraie, "Hardware considerations for
digital audio broadcasting system," Proc. IEEE International Conference on
Microelectronics 2005, pp. 209-212, Pakistan, Dec. 2005.
[104] S. M. Mortazavi Zanjani, S. M. Fakhraie, and O. Shoaei, "A comparative study and design
of decimation filter for high-precision audio data converters," Proc. IEEE International
Conference on Microelectronics 2005, pp. 139-143, Pakistan, Dec. 2005.
[105] M. Nazm-Bojnordi, N. Sedaghati-Mokhtari, and S. Mehdi Fakhraie, "A self-testing fully
pipelined implementation for the advanced encryption standard," Proc. IEEE International
Conference on Microelectronics 2005, pp. 260-263, Pakistan, Dec. 2005.
[106] N. Moezzi Madani, J. Hadi, and S. Mehdi Fakhraie, "Design and implementation of a fully
digital 4FSK demodulator," Proc. European Conference on Circuit Theory and Design,
pp. 277-280, Ireland, Dec. 2005.
[107] A. Banaiyan, H.R. Mahdiani, and S.M. Fakhraie, "Cost-performance co-analysis in VLSI
implementation of existing and new defuzzification methods," Proc. International
Conference on Computational Intelligence for Modeling Control and Automation –
CIMCA, Austria, Nov. 2005.
[108] E. Rohani and S. M. Fakhraie, "Reducing round-off error in an ADSL modem with blockfloating-point
structure," in Proc. International Symposium on Telecommunications
(IST2005), Shiraz, Iran, Sep. 2005.

[109] M. Alisafaee, S. Ataee, S. M. Fakhraie, "Bandwidth-enhanced waste-free control technique
for multi-queue network buffers," in Proc. International Symposium on
Telecommunications (IST2005), Shiraz, Iran, Sep. 2005.
[110] G. R. Chaji and S. M. Fakhraie, "A low-power high-performance digital circuit for deep
submicron technologies," in Proc. IEEE NEWCAS05, Quebec, Canada, June 19-22, 2005.
[111] M. Alisafaee, and S. M. Fakhraie, Mohammad Tehranipoor "Architecture of an embedded
queue management engine for high-speed network devices," in Proc. 2005 IEEE Int’l
Midwest Symposium on Circuits and Systems, Cincinnati, USA, Aug. 2005.
[112] Hadi Esmaeilzadeh, Farhang Farzan, Neda Shahidi, Sied Mehdi Fakhraie, Caro Lucas, and
Mohammad Tehranipoor, " NnSP: Embedded neural networks stream processor," in Proc.
2005 IEEE Int’l Midwest Symposium on Circuits and Systems, Cincinnati, USA, Aug.
2005.
[113] Saeed Shamshiri, S. Mehdi Fakhraie, and Zainalabedin Navabi, "Designing optimal
forwarding tables with genetic algorithm," Proc. ACM SIGCOMM Workshop 2005,
Beijing, China, April 2005.
[114] Mehdi Salmani Jelodar, Sied Mehdi Fakhraie, and Majid Nili Ahmadabadi, "A new
approach for training of artificial neural networks using population based incremental
learning (PIBL), Proc. of the Int. Conf. Computational Intelligence (ICCI 2004),
Istanbul, Turkey, pp. 165-168, Dec. 2004.
[115] Hadi Esmaeilzadeh, Hamed Farshbaf, Caro Lucas, and Sied Mehdi Fakhraie, "Digital
implementation for conic section function networks," Proc. IEEE Int. Conf.
Microelectronics 2004 (ICM2004), Tunis, Tunisia, pp. 564-567, Dec. 2004.
[116] S. Shamshiri, and Sied Mehdi Fakhraie, "Parallel alias reduction for MP3 decoding," Proc.
IEEE Int. Conf. Microelectronics 2004 (ICM2004), Tunis, Tunisia, pp. 438-441, Dec.
2004.
[117] M. Ghannad Rezaie, F. Farbiz, and Sied Mehdi Fakhraie, "An analytical approach to
hardware-friendly adaptive learning rate neural networks," Proc. IEEE Int. Conf.
Microelectronics 2004 (ICM2004), Tunis, Tunisia, pp. 320-323, Dec. 2004.
[118] S. Shamshiri, S. Mehdi Fakhraie, and C. Lucas, "A genetic algorithm solution for
designing optimal forwardign tables," Proc. Sixth Conf. Intelligent Systems (CIS 2004),
Kerman, Iran, Nov. 2004.
[119] S. R. Abdollahi, S. M. Fakhraie, M. Kamaeri, and S. E. Abdollahi, "A 68MHz multichannel
all-digital programmable oscillator," Proceedings 2003 10th IEEE International
Conference on Electronics, Circuits and Systems, 2003 (ICECS 2003),vol. 2 , pp. 475-
478, 14-17 Dec. 2003.
[120] S. R. Abdollahi, M. Kamaeri, and S. M. Fakhraie, "Semi-coherent GFSK receiver for
DECT standard," Proceedings 2003 10th IEEE International Conference on
Electronics, Circuits and Systems, 2003 (ICECS 2003),vol. 3 , pp. 1244-1247, 14-17
Dec. 2003.
[121] Seyed Reza Abdollahi, Seyed Mehdi Fakhraei, Bertan Bakkaloglu, and Mahmoud
Kamarei, "A crystal-based digital ring oscillator," Proceedings 2003 IEEE International
Conference on Field-Programmable Technology (FPT), Tokyo, Japan, pp. 319-323,
Dec. 15-17, 2003.
[122] Mohammad Tehranipour, Mehrdad Nourani, Mehdi Fakhraie, and Ali Afzali-Kusha,
“Systematic test program generation for SoC testing using embedded processors,” ISCAS
2003, Bangkok, Thailand, vol. 5, pp. 541-544, May 2003.
[123] G. R. Chaji, R. M. Pourrad, S. M. Fakhraie, and M. H. Tehranipour, “EUTDSP: A design
study of a new VLIW-based DSP architecture,” ISCAS 2003, Bangkok, Thailand, vol. 4,
pp. 137-140, May 2003.

[124] S. M. Fakhraie, M. H. Tehranipour, M. R. Movahedin, and M. Nourani, "Fast prototyping
of a DSP core," 45th Midwest Symposium on Circuits and Systems, vol. 2, Page(s): 215
-218, 2002.
[125] M. H. Tehranipour, M. Nourani, S. M. Fakhraie, and C. A. Papachristou, "Test
optimization of bus-structured SoCs using embedded processor," 45th Midwest
Symposium on Circuits and Systems, vol. 1, Page(s): 168-171, 2002.
[126] R. Rafati, A. Z. Charaki, G. R. Chaji, S. M. Fakhraie, and K. C. Smith, “Comparison of a
17b multiplier in dual-rail Domino and dual-rail D3L logic styles,” ISCAS 2002,
Scottsdale, Arizona, vol. 3, pp. 257-260, May 26-29 2002.
[127] G. R. Chaji, S. M. Fakhraie, and K. C. Smith, “Pseudo dynamic logic (SDL): A highspeed
and low-power logic family,” ISCAS 2002, Scottsdale, Arizona, vol. 3, pp. 245-248,
May 26-29 2002.
[128] S. R. Abdollahi, S. M. Fakhraie, and Sayfe Kiaei, “An all-digital programmable digitallycontrolled-oscillator
(DCO) for digital wireless applications,” ISCAS 2002, Scottsdale,
Arizona, vol. 4, pp. 101-104, May 26-29 2002.
[129] G. R. Chaji, S. M. Fakhraie, and K. C. Smith, “High-speed low-power adder design with a
new logic style: Pseudo Dynamic Logic (SDL),” Proc. IEEE Int. Conf. Microelectronics
2001 (ICM2001), (Rabat, Morocco), Oct.29-31 2001.
[130] H. R. Mahdiany, A. Hormati, and S. M. Fakhraie, “A hardware accelerator for DSP system
design: University of Tehran DSP hardware emulator (UTDHE),” Proc. IEEE Int. Conf.
Microelectronics 2001 (ICM2001), (Rabat, Morocco), Oct.29-31 2001.
[131] M. Tehranipour, Z. Navabi, and S. M. Fakhraie, “A low-cost BIST architecture for
microprocessor/DSP cores,” Proc. Third Electronics Circuits and Systems Conf.
(ECS’01), (Bratislava, Slovakia), Sep. 5-7 2001.
[132] H. Zarei, O. Shoaei, and S. M. Fakhraie, “A low-power fully integrated Gaussian-MSK
modulator based on the sigma-delta fractional-N frequency synthesis,” Proc. ISCAS 2001
(Sydney, Australia), vol. 4, pp. 100-103, May 2001.
[133] M. Tehranipour, Z. Navabi, and S. M. Fakhraie, “An efficient BIST method for testing of
embedded SRAMs,” in Proc. ISCAS 2001, (Sydney, Australia), vol. 5, pp. 73-76, 6-9 May
2001.
[134] H. Zarei, O. Shoaei, S. M. Fakhraie, and M. M. Zakeri, “A 1.4 GHz/ 2.7 V programmable
frequency divider for DRRS standard in 0.6 /spl mu/m CMOS process,” Proc. 7th IEEE
International Conference on Electronics, Circuits and Systems, 2000, (ICECS 2000),
(Jounieh, Lebanon), vol. 2, pp. 887 –890, Dec. 2000.
[135] S. R. Abdollahi, S. M. Fakhrai, and M. M. Zakeri, “Performance of phase locked loop
GFSK demodulator in a multipath channel,” in Proc. 3rd Int. Symp. Wireless Personal
Multimedia Communications (WPMC’00), (Bangkok, Thailand), pp. 825-829, Nov. 12-
15, 2000.
[136] S. A. Khodaian, S. H. Jamali, R. Hoshyar, S. M Fakhrai, and A. S. Bahai, “Threshold
LogMAP SISO block for FPGA implementation of turbo decoder,” in Proc. 3rd Int.
Symp. Wireless Personal Multimedia Communications (WPMC’00), (Bangkok,
Thailand), pp. 538-542, Nov. 12-15, 2000.
R. Rafati, A. Z. Charaki, S. M. Fakhraie, and K. C. Smith, “Data-driven dynamic logic versus
NP-CMOS logic, a comparison,” in Proc. Twelfth IEEE Int. Conf. Microelectronics
(ICM’2000), (Tehran, Iran), pp. 57-60, Oct. 31-Nov. 2, 2000.
[137] Mehran Nadjarbashi, S. Mehdi Fakhraie, and Alireza Kaviani, “On routing structure for the
hybrid field programmable architecture,” Proc. Twelfth IEEE Int. Conf.
Microelectronics (ICM’2000), (Tehran, Iran), pp. 259-264, Oct. 31-Nov. 2, 2000.

[138] Hossein Zarei, Omid Shoaei, S. M. Fakhraie, and M. M. Zakeri, “A low-power multimodulus
divider in 0.6um digital CMOS technology,” Proc. Twelfth IEEE Int. Conf.
Microelectronics (ICM’2000), (Tehran, Iran), pp. 359-362, Oct. 31-Nov. 2, 2000.
[139] M. Haji-rostam, M. Maddah-Ali, A. Haft-Baradaran, M. T. Kilani, S. M. Fakhraie, M.
Sharifkhani, and O. Shoaei, “Kalman-filtering timing recovery scheme for orthogonal
frequency domain multiplexing (OFDM) systems,” in Proc. ICASSP’2000, (Istanbul,
Turkey), pp. V-2681-2684, June 5-9 2000.
[140] R. Rafati, S. M. Fakhraie, and K. C. Smith, “Low-power data-driven dynamic logic
(D3L),” in Proc. ISCAS’2000, (Geneva, Switzerland), pp. I-752-755, 28-31 May 2000.
[141] F. Bahmani, S. M. Fakhraie, and A. Khakifirooz, “A rail-to-rail one-Volt constant-Gm
CMOS opamp,” in Proc. ISCAS’2000, (Geneva, Switzerland), pp. II-669-672, 28-31 May
2000.
[142] A. Kheirkhahi, S. M. Fakhraie, and M. Kamarei, “Algorithmic design of a 900 MHz
CMOS RF power amplifier introducing SPICE-Smith chart method,” Proc. European
Solid State Circuits Conference 1999 (ESSCIRC’99), (Germany), 17-20 Sept. 1999.
[143] O. Nasibi, M. Nourani, S. M. Fakhraie, A. Zakeri, and A. Ghalambor-Dezfoli, “Multiaccess
integrated memory management for deeply-pipelined processors,” Proc. Eleventh
IEEE Int. Conf. Microelectronics (ICM’99), (Kuwait), pp. 285-289, 22-24 Nov. 1999.
[144] M. Samady, M. Movahedin, S. M. Fakhraie, Z. Navabi, and A. Ghalambor-Dezfoli,
“Implementation of serial port interconnections for integrated circuits,” Proc. Eleventh
IEEE Int. Conf. Microelectronics (ICM’99), (Kuwait), pp. 291-294, 22-24 Nov. 1999.
[145] A. Kheirkhahi, S. M. Fakhraie, and M. Kamarei, “A low-voltage high efficiency digitally
programmable DC/DC converter,” Proc. Eleventh IEEE Int. Conf. Microelectronics
(ICM’99), (Kuwait), pp. 281-284, 22-24 Nov. 1999.
[146] F. Bahmany and S. M. Fakhraie, “A rail-to-rail 1-Volt CMOS opamp,” Proc. Eleventh
IEEE Int. Conf. Microelectronics (ICM’99), (Kuwait), pp. 217-219, 22-24 Nov. 1999.
[147] A. Sodagar, S. M. Fakhraie, and K. C. Smith, “A low-voltage Current-Controlled
Oscillator with low supply dependency,” Proc. Tenth IEEE Int. Conf. Microelectronics
(ICM’98), (Monastir, Tunisia), pp. 282-285, Dec. 14-16, 1998.
[148] A. H. Abutalebi and S. M. Fakhraie, “A submicron analog neural network with an
adjustable-level output unit,” Proc. Tenth IEEE Int. Conf. Microelectronics (ICM’98),
(Monastir, Tunisia), pp. 294-297, Dec. 14-16, 1998.
[149] F. Baharvand and S. M. Fakhraie, “A reduced lookup table for SRAM-based FPGA logic
blocks,” Proc. Ninth IEEE Int. Conf. Microelectronics (ICM’97), (Bandung, Indonesia),
pp. 138-141, Oct. 8-10, 1997.
[150] A. H. Abutalebi and S. M. Fakhraie, “Submicron analog multipliers: Overview,
comparison, and modelling,” Proc. Ninth IEEE Int. Conf. Microelectronics (ICM’97),
(Bandung, Indonesia), pp. 85-88, Oct. 8-10, 1997.
[151] S. Mehdi Fakhraie, J. M. Xu, and K. C. Smith, “Design and implementation of
SynapseMOS (SyMOS) Artificial Neural Networks,” Proc. Eighth Int. Conf.
Microelectronics (ICM’96), (Cairo, Egypt), pp. 71-74, Dec. 14-16, 1996.
[152] S. Mehdi Fakhraie, J. M. Xu, and K. C. Smith, “Application of analog quadratic neural
networks (AQNNs) to function approximation problems,” Proc. Int. Conf. Intelligent and
Cognitive Systems, (Tehran, Iran), pp. 43-48, Sep. 1996.
[153] S. Mehdi Fakhraie, J. M. Xu, and K. C. Smith, “Design of CMOS Quadratic Neural
Networks,” Proc. IEEE Pacific Rim Conf. on Communications, Computers, and Signal
Processing, (Victoria, BC, Canada) May 17-19, 1995.

[154] S. Mehdi Fakhraie, K. C. Smith, and J. M. Xu, “Comparison of three different architectures
for MOS-Compatible quadratic synapses,” Proc. IEEE Int. Symp. Speech, Image
Processing, and Neural Networks, (Hong Kong), pp. 483-6, April 13-16, 1994.
[155] S. Mehdi Fakhraie and K. C. Smith, “Synapse-MOS (SyMOS) Transistors: Intelligent
MOS transistors with learning thresholds,” Proc. Canadian Conf. VLSI’93 (Banff,
Alberta, Canada), pp. 7.28-33, Nov. 14-16, 1993.
[156] S. Mehdi Fakhraie, A. Konrad, and K. C. Smith, “Application of neuro-computation
techniques to sampled-data electromagnetic-field problems,” Records of the Ninth
COMPUMAG Conf., (Miami, Florida), pp. 72-73, Nov. 1993.
[157] S. Mehdi Fakhraie and K. C. Smith, “Generalized artificial neural networks,” Proc.
Canadian Conf. Elec. and Comp. Eng. (Vancouver, BC, Canada), pp. 469-472, Sept. 14-
17, 1993.

Reviewed Conference Papers (Published in the Proceedings of Local Conferences):
[158] Z. Pajouhi and S. M. Fakhraie, “A new technique for implementation of continuous-time
digital signal processing,” in Proc. 18 th Iranian Conf. Electrical Engineering
(ICEE2010), Isfahan, Iran, May 2010.
[159] S. Rahmanian, S. M. Fakhraie, and A. Nabavi, “Optimal bit-true model for implementation
of a digital audio broadcasting OFDM system,” in Proc. 17 th Iranian Conf. Electrical
Engineering (ICEE2009), Tehran, Iran, 12-14 May 2009.
[160] Mohammad Reza Ghaderi, Omid Shoaei, and Sied Mehdei Fakhraie, “A novel ultra-lowvoltage
CMOS RF-DC converter for long range passive RFID applications,” in Proc. 16 th
Iranian Conf. Electrical Engineering (ICEE2008), Tehran, Iran, 2008.
[161] E. Rahmani, S. M. Fakhraie, and M. Kamarei, “Design and modeling of physical layer of
IEEE 802.15.4 standard,” in Proc. 15 th Iranian Conf. Electrical Engineering
(ICEE2007), Tehran, Iran, 15-17 May 2007, (in Farsi).
[162] M. Nabipoor, S. A. Khodaian, S. Rahmanian, and S. M. Fakhraie, “Hardware consideration
for Soft-Input Soft-Output (SISO) block of turbo decoder,” in Proc. 15 th Iranian Conf.
Electrical Engineering (ICEE2007), Tehran, Iran, 15-17 May 2007.
[163] Z. Pajouhi and S. M. Fakhraie, “Performance analysis of a time-domain equalizer in a
WiMax system,” in Proc. 15 th Iranian Conf. Electrical Engineering (ICEE2007),
Tehran, Iran, 15-17 May 2007.
[164] M. E. Salehi, A. Hormati, A. Banaiyan, and S. M. Fakhraie, “A proposed architecture for
layer-2 packet processing,” in Proc. 15 th Iranian Conf. Electrical Engineering
(ICEE2007), Tehran, Iran, 15-17 May 2007.
[165] A. Farmahini-Farahani and S. M. Fakhraie, “SOPC-based particle swarm optimization," in
Proc. 12 th International CSI Computer Conference (CSICC' 2007), Tehran, Iran, Feb.
2007.
[166] P. Saeedy and S. M. Fakhraie, "Co-processor for genetic algorithms," in Proc. 14 th Iranian
Conf. Electrical Engineering (ICEE2006), Tehran, Iran, April 2006.
[167] N. Sedaghati-Mokhtari, S. Rahmanian, and S. M. Fakhraie, "Hardware implementation
analysis for digital filters," in Proc. 14 th Iranian Conf. Electrical Engineering
(ICEE2006), Tehran, Iran, April 2006.
[168] M. Salehi, M. Najibi, H. Pedram, A. Afzali-Kousha, and S. M. Fakhraie, "Implementation
of dynamic control system for voltage and frequency for power reduction of processors," in
Proc. 14 th Iranian Conf. Electrical Engineering (ICEE2006), Tehran, Iran, April 2006
(in Persian).
[169] M. Salmani Jelodar, H. Kamal, S. M. Fakhraie, and M. Nili Ahmadabadi, "SOPC-based
parallel genetic algorithm," in Proc. 14 th Iranian Conf. Electrical Engineering
(ICEE2006), Tehran, Iran, April 2006.
[170] Sedigheh Hashemi and S. M. Fakhraie, "A novel technique for design and optimization of
FIR digital filters using genetic algorithms," in Proc. 14 th Iranian Conf. Electrical
Engineering (ICEE2006), Tehran, Iran, April 2006.
[171] H. Parande Afshar and S. Mehdi Fakhraie, "Parallel merged multiplier-accumulator
coprocessor optimized for audio filters," in Proc. 11 th International CSI Computer
Conference (CSICC' 2006), Tehran, Iran, Jan. 2006.
[172] M. Salmani Jelodar, S. Mehdi Fakhraie, M. Nili Ahmadabadi, "Improving morphological
filters by intelligent algorithms," in Proc. Conf. Computational Intelligence, Tehran, Iran,
2005.

[173] H. Esmailzadeh, A. Pedram, A. Alaghi, B. N. Araabi, C. Lucas, and S. M. Fakhraie,
"Neural network parallel data flow processor architecture," Proc. 13 th Iranian Conf.
Electrical Engineering (ICEE2005), Zanjan, Iran, May 2005.
[174] M. B. Vahidfar, S. M. Fakhraie, and M. Fardis, "Delta sigma enhanced, low SFDR, area
efficient digital FM modulator," Proc. 13 th Iranian Conf. Electrical Engineering
(ICEE2005), Zanjan, Iran, vol. 1, pp. 427-430, May 2005.
[175] M. AliSafaee and S. M. Fakhraie, "Design and alalysis of a double bandwidth memory for
network routers and switches," Proc. 13 th Iranian Conf. Electrical Engineering
(ICEE2005), Zanjan, Iran, May 2005 (in Persian).
[176] M. Alisafaee, Z. Navabi, and S. M. Fakhraie, "Doubling memory bandwidth for singlequeue
network buffers using uniform distribution methods," Proc. 10 th Annual CSI Conf.
(CSICC'2005), Tehran, Iran, pp. 172-179, Feb. 2005.
[177] H. Kalantari, H. pedram, and S. M. Fakhraie, "A methof for high-level energy estimation
in template-based QDI asynchronous circuits," Proc. 10 th Annual CSI Conf.
(CSICC'2005), Tehran, Iran, pp. 180-187, Feb. 2005.
[178] S. shamshiri and S. M. Fakhraie, "Enhanced full expansion compression method for fast IP
address lookup with minimum memory consumption," Proc. 10 th Annual CSI Conf.
(CSICC'2005), Tehran, Iran, pp. 212-221, Feb. 2005.
[179] M. Haji-Rostam, M. A. Maddah-Ali, A. Haft-Baradaran, M. T. Kilani, S. M. Fakhraie, M.
Sharifkhani, and O. Shoaei, “A robust timing recovery scheme based on Kalman-filtering
for OFDM systems,” Proc. Eighth Iranian Conf. Electrical Engineering, (Isfahan, Iran),
pp. vol. 4, pp. 87-92, May 17-19, 2000.
[180] M. Haji-Rostam, M. Sharifkhani, A. Haft-Baradaran, M. T. Kilani, O. Shoaei, S. M.
Fakhraie, and A. Adibi, “System design of an ADSL modem based on ANSI T1.413,”
Proc. Eighth Iranian Conf. Electrical Engineering, (Isfahan, Iran), vol. 4, pp. 173-180,
May 17-19, 2000.
[181] H. Zarei, M. M. Zakeri, O. Shoaei, and S. M. Fakhraie, “Design of a multi-modulus
fractional-N low-power high-speed frequency divider,” Proc. Eighth Iranian Conf.
Electrical Engineering, (Isfahan, Iran), May 17-19, 2000.
[182] R. Rafati and S. M. Fakhraie, “Data-driven dynamic logic (D3L),” Proc. Seventh Iranian
Conf. Electrical Engineering, (Tehran, Iran), pp. Ele. 61-68, 17-19 May, 1999.
[183] A. Kheirkhahi, S. M. Fakhraie, M. Kamarei, “Design of CMOS-RF power amplifiers using
SPICE-Smith chart method,” Proc. Seventh Iranian Conf. Electrical Engineering,
(Tehran, Iran), pp. Ele.29-36, 17-19 May, 1999.
[184] M. Samady, S. M. Fakhraie, Z. Navabi, and A. Ghalambor-Dezfoli, “Modelling and
hardware implementation of a FIR filter with programmable architecture,” Proc. Seventh
Iranian Conf. Electrical Engineering, (Tehran, Iran), 17-19 May, 1999.
[185] B. Sajadi-Birea and S. M. Fakhraie, “Application of generalization-enhancement
techniques to hand-written character recognition,” Proc. Fourth Annual International
Conf. Computer Society of Iran, (Tehran, Iran), Dec. 23-25, 1998.
[186] A. H. Abutalebi and S. M. Fakhraie, “Universal characterization of a basic differential
stage and a Gilbert multiplier by a general functional MOS model,” Proc. Sixth Iranian
Conf. Electrical Engineering, (Tehran, Iran), pp. III67-72, 12-14 May, 1998.
[187] A. Sodagar and S. M. Fakhraie, “Design of a digital CCO with low supply dependency,”
Proc. Sixth Iranian Conf. Electrical Engineering, (Tehran, Iran), pp. III73-77, 12-14
May, 1998.
[188] S. Safari and S. M. Fakhraie, “Design of a hardware accelerator for Viterbi algorithm,”
Proc. Sixth Iranian Conf. Electrical Engineering, (Tehran, Iran), pp. III99-104, 12-14
May, 1998.

[189] B. Sajadi-Birea and S. M. Fakhraie, “A generalization enhancement method for artificial
neural networks in function approximation applications,” Proc. Sixth Iranian Conf.
Electrical Engineering, (Tehran, Iran), 12-14 May, 1998.
[190] F. Baharvand and S. M. Fakhraie, “Design of an optimized architecture for the logic blocks
of FPGA ICs,” Proc. Third Annual International Conf. Computer Society of Iran,
(Tehran, Iran), pp. 206-214, Dec. 23-25, 1997.
[191] B. Alizadeh, S. M. Fakhraie, and Z. Navabi, “Rapid design of complex VLSI systems by
using a multi-level simulation environment in VHDL,” Proc. Third Annual International
Conf. Computer Society of Iran, (Tehran, Iran), pp. 221-228, Dec. 23-25, 1997.
[192] Atid Shamaie, S. M. Fakhraie, and B. Benhabib, “Accurate estimation of partly-occluded
ellipse Parameters,” Proc. Fifth Iranian Conf. on Electrical Engineering, (Tehran, Iran),
pp. 5-24-33, May 7-9, 1997.
[193] F. Baharvand, and S. M. Fakhraie, “On designing reduced lookup tables for logic blocks of
SRAM-based FPGAs,” Proc. Fifth Iranian Conf. on Electrical Engineering, (Tehran,
Iran), pp. 1-178-186, May 7-9, 1997.
[194] S. Mehdi Fakhraie, J.M. Xu, and K.C. Smith, “Design of a new class of CMOS-compatible
artificial neural networks,” Proc. Fourth Iranian Conf. on Electrical Engineering,
(Tehran, Iran), pp. 489-97, May 1996.
[195] A. Khalili, S. Mehdi Fakhraie, “A compact serial/parallel systolic array multiplier,” Proc.
Second CSI Computer Conference (CSICC’96), (Tehran, Iran), pp. 132-7, Dec. 24-26,
1996.

Summary of Academic Activities of S. Mehdi Fakhraie
Academic Activities at School of Electrical and Computer Engineering,
the University of Tehran
Undergraduate Courses Taught:
At ECE Department of the University of Tehran my undergraduate courses were running for
sixteen weeks before exams. Each course was complemented with regular weekly assignments
and biweekly mini-projects. Normally a larger project was given towards the end of the term.
With final exam, midterm, and several quizzes, students had more than twenty marks, out of
which their course marks were given.
Electronic Circuits
Major reference: “Microelectronic Circuits,” by A. Sedra, and K. C. Smith.
Digital Electronics
Major references: “Digital Integrated Circuits,” by J. Rabaey, and “Digital Integrated System
Design,” by Kenneth W. Martin.
Computer-Aided Design and FPGA Implementation of Digital Circuits
Major reference: “Verilog Digital System Design,” by Z. Navabi, notes prepared on FPGA and
CPLD architectures from various tutorials and data sheets and manuals from Xilinx, Altera, and
other FPGA companies.
Design of VLSI Systems
Major references: “Principles of CMOS VLSI Design,” by Neil H. E. Weste, and D. Harris;
“Digital Integrated Circuits,” by J. Rabaey, and my personal tutorial notes on VLSI CAD tool
usage and Verilog modeling of VLSI systems. Sets of lab tutorials were prepared for the class
with dedicated set of notes.
Graduate Courses Taught:
Graduate courses were composed of 16 weeks of classes. From 1995 to 1998, instructors were
allowed to assign one-year-long projects for selected core graduate courses, but later this period
was limited to one term after the classes were completed. My graduate courses were normally
coming with extensive course projects besides regular assignments, one or two presentations, and
a term paper.
Advanced VLSI Design
Major references: “Principles of CMOS VLSI Design,” by Neil H. E. Weste, and D. Harris;
“Digital Integrated Circuits,” by J. Rabaey, “Digital Systems design with VHDL and synthesis,”
by K. C. Chang, Proceedings of each year’s ISSCC conference, and my personal tutorial notes on
VLSI CAD tool usage and Verilog modeling of VLSI systems. Sets of lab tutorials were prepared
for the class with dedicated set of notes.
This was one the major and mandatory courses for Computer Engineering and Electronic
graduate students. Parallel lab sessions on CAD tool usage were running for students. Miniprojects
on major concepts were assigned. At the end of the classes, the students were expected
to present one of ISSCC papers in class final presentations and present a term paper. After final
exam, students were asked to complete one full VLSI-design cycle down to layout on selected
projects that were assigned with mutual agreements of the students and the instructor. Some of

the students were normally assigned on extensive team-based projects such as design of IPs for
peripherals and core of a MIPS-based CPU for embedded system design, design of a complete
DSP processor and its peripherals, implementation of an ADSL modem, etc. In these extended
teamwork projects that were normally based on VLSI lab projects, researchers and senior
graduate students of VLSI lab were asked to assist students to fulfill their assignments.
Design of ASIC CMOS Systems
Major References: M. S. Smith, Application-Specific Integrated Circuits, Addison-Wesley, 1997.
N. E. Weste, and K. Eshraghian, Principles of CMOS VLSI Design. Addison-Wesley, 2001. Jan M. Rabaey,
A. Chandrakasan, B. Nicolic, Digital Integrated Circuits, A Design Perspective, Prentice Hall,
New Jersey, 2003. Class notes and lab handouts.
This course discusses the design flow and associated procedures and CAD tools required in
execution of an ASIC design project. Emphasis is given to full- and Semi-custom CMOS design.
We briefly review CMOS technology and design styles, and then go over library preparation, and
environment setup for database and designer synchronization in a distributed team. After a brief
review over FPGA implementation options, we continue our journey in the CMOS design world
by going deeper into design flow and CAD tools as listed in the outline below. At the end, we
give references for some of the more critical contemporary issues in operation of complex
systems including reset and clocking alternatives and their comparison.
Custom Inplementation of DSP Systems
Major references: Lars Wanhammer, DSP Integrated Circuits. Academic Press, San Diego, 1999.
Keshab K. Parhi, VLSI Signal Processing Systems, Design and Implementation. John Wiley &
Sons, Inc., New York, 1999. A. V. Oppenheim, R. W. Shafer, Discrete-Time Signal Processing.
Prentice Hall, Englewood Cliffs, NJ, 1995.
Intention of this course is to describe the procedures involved in optimum implementation of
DSP systems, where for cost, area, power, and performance reasons, we have to explore the
extremes of the possibilities in a given CMOS implementation technology.
Design of Dedicated Processors for Intelligent Systems
Major references: “VLSI-Compatible Implementations for Artificial Neural Networks,” by S.
Mehdi Fakhraie, K. C. Smith, and a set of journal and conference papers.
This course was based on my own research on implementation of neural networks and intelligent
systems. Students were starting with a C-language programming project at the beginning of the
term while I was introducing major neural computation concepts to them. By implementing a
modular system in software, they were ready for starting to observe and investigate how those
modules and concepts could be implemented in hardware. Then the class continues by review of
implementation approaches for different types of blocks and modules and then major works in
the field were reviewed and re-designed by the students.
BiCMOS Integrated Circuits
Major references: “Digital BiCMOS Integrated Circuit Design,” by S. H. K. Embabi, A.
Bellaouar, and M. I. Elmasry, with a set of conference tutorials and journal papers. This course
was taught during the years of 1995 to 1997.

RF Integrated Circuits
Major references:” RF Microelectronics,” by B. Razavi, and “The Design of CMOS Radio-
Frequency Integrated Circuits,” by Thomas H. Lee.
I taught this course once when I was designing a frontend IC for an integrated pager receiver in
1998.
Array Processors
Major references: “VLSI Array Processors,” by S. Y. Kung, and personal notes.
Taught from 1995 till 1998.
Parallel Processing
Major references: "Introduction to Parallel Computing," by A. Grama, A. Gupta, G.Karypis, and
V. Kumar; "Introduction to Parallel Processing: Algorithma and Architectures." By B. Parhami,
and “The Grid: Blueprint for a New Computing Infrastructure,” by I. Foster, and C. Kesselman;
notes and manuals on PVM, and MPI environments and libraries, and related journal papers.
Graduate Theses Supervised:
In Electronics and Computer Engineering Groups, I have advised and co-supervised around sixty
graduate students. Their theses have been defined in response to industrial projects of VLSI Lab
and Silicon Intalligence and VLSI Signal Processing lab (SILab), and/or our academic theoretical
developments. They have been working in one of the labs that I and group of other colleagues
have established here. In the area of VLSI Design emphasis has been given on development of
novel high-speed and low-power digital logic circuits and design of integrated systems. Activities
in the SILab are concentrated on development of new intelligent signal processing algorithms and
exploration of new implementations for them. Here, I am listing only those students that have
completed their theses in VLSI or SI labs while I have been their main advisor, or major thesis
contributor.
Graduated Students
No. Student Degree Thesis Title
61
Mehdi Ahmadi M.Sc.
Proposed Model and Bit-True Design of Physical
Advisor
Layer of IEEE 802.22
60 Amir
Yazdanbakhsh
59 Hamid Reza
Mahdiani
M.Sc. Advisor
Ph.D. Advisor
Integrated Platform for Modelling and Simulation of
Embedded Processors with Emphasis on Network
Processors
Considerations for Implementation of Intelligent
Systems in Nano Technologies
58
Zohreh Sharifi M.Sc.
Bit-True Modeling and Implementation of Wideband
Advisor
Codecs
57
Analysis and Development of Fault-Tolerant Design
Farshad Firouzi M.Sc. Advisor Techniques for Network Processors in Nano-Scale
implementations

56
Shervin Vakili M.Sc. Advisor
Design and Implementation of an NoC-based Scalable
Cellular Architecture
55 Ashkan Jalili M.Sc. Advisor Bit True Modelling of IEEE 802.20 Standard with
Consideration of Implementation Challenges
54 Mehrdad
Ghobady
M.Sc. Advisor
Low Complexity Techniques for Digital Signal
Processing Systems Design
53 Ali Ahmadi M.Sc. Advisor Fault Tolerant Hardware Implementation of Artificial
Neural Networks
52 Rasoul Yousefi M.Sc. Advisor Low-Cost Concurrent Test of Digital Signal
Processing Systems
51
Faeze Montazary M.Sc. Advisor
A High Performance Evolutionary Framework for
System Design
50 Amir Moghimi M.Sc. Advisor Transactional Memory NoC Embedded System
Design
49 Mohammad-
Reza Ghaderi
Garakani
M.Sc. Advisor Integrated Design of a UHF Passive RFID Tag
48 Mahdi Hamze M.Sc. Advisor Design and Implementation of a Fuzzy Processor for
Reat-Time Systems
47 Amin Farmahini
Farahani
46
45
M.Sc. Advisor
Pooya Saeedy M.Sc. Advisor
Fatemeh Kashfi M.Sc. Advisor
44 Neda Kazemian
Amiri
43 Naser-adin
Sedaghati-
Mokhtari
M.Sc. Advisor
M.Sc. Advisor
Design and Implementation of Hardware Cores for
Bio-Inspired Algorithms
NoC Systems in High Performance MultiProcessor
Environments
Design of Low-Power High-Speed Computational
Systems in below-70nm Technologies
Design of Optimum Hardware Engine for Efficient
Implementation of Voice Codecs in Poratable Devices
Design of Parallel VLIW Architecture for VoIP
Applications
42 Ahmad Saghafi M.Sc. Advisor Baseband Design of a UWB Receiver with Reduced
Power and Complexity
41 Shahab-adin
Rahmanian
M.Sc. Advisor
Design and Modeling of Baseband Part of IBOC-DAB
Transceiver
40 Elaheh Rahmani M.Sc. Advisor Low-Power Core for Zigbee System
39
Zoha Pajouhi M.Sc.
Design and Realization of Baseband Module of Next
Advisor
Generation MIMO WLAN Systems
38 Somayeh
M.Sc.
Rahimian Omam
Advisor Design of DSP Part of a High-speed ADC

37 Sayedeh
Maryam
Mortazavi
Zanjani
M.Sc. Advisor Design of Digital Part of a High-speed DAC
36 Ardavan Pedram M.Sc. Advisor Implementation of a LOLIMOT Fuzzy Neuron
35 Ehsan Rohani M.Sc. Advisor System Level Design of Baseband Module of 802.16
34 Mahdi Salmani-
Jelodar
M.Sc. Advisor
Efficient Realization of Bio-Inspired Genetic
Algorithms
33 Abbas Banayian M.Sc. Advisor Efficient Fuzzy Rule Implementation
32 Nariman
M.Sc.
Moezzi-Madani
Advisor Realization of DAB System
31 Hamed Holisaz M.Sc. Advisor SoC Design for MAC Layer of 802.16
30 Hadi
Esmailzadeh
M.Sc. Advisor Neural Network Stream Processor
29 Mohammad Ali-
Safaie
M.Sc.
High-Speed Memory Management for Network
Advisor
Processors
28
Saeed Shamshiri M.Sc.
High-Speed IP Lookup for Next Generation Network
Advisor
Devices
27
Amir Javanpak M.Sc.
Implementation ADSL Modem on C6x DSP With
Advisor
Increased Bit Rate
26 Mohammad
Nabipour
M.Sc. Advisor VLSI implementation of Turbo-Codes
25
Hamed Farshbaf M.Sc.
Digital Implementation for Conic Section Neural
Advisor
Networks
24 Reza
Design of a DSP processor with VLIW architecture,
Mohammad M.Sc. Advisor optimized for low power applications. (Having
Pour Rad
instructions compatible with TI’s TMS320C6X)
23
Bita Gorji Ara M.Sc.
A Generic Re-configurable Distributed Framework for
Advisor
VLSI CAD Applications
22 Pedram Arshad
Riahi
M.Sc.
Coadvisor
RUTS-DSP: RISC Enhanced Version of UTS CISC
DSP Processor
21 Ramin Rafati M.Sc. Advisor Data-Driven-Dynamic Logic (D 3 L)
20 Sayed Ali Hejazi M.Sc. Advisor Design of Fully-CMOS Paging Frontend
19 Ali Haj
Abutalebi
M.Sc. Advisor Design of Sub-micron Analog Neural Networks
18 Mohammad
Hossein
Tehranipour
M.Sc.
Coadvisor
Implementation of an Efficient BIST Architecture on
UTS-DSP

17 Ali-Reza
Khairkhahi
16 Faramarz
Bahmani
15 Sayed Reza
Abdollahi
14 Gholam Reza
Chaji
13 Hamid Reza
Mahdiani
M.Sc. Advisor
Full CMOS Class E Power Amplifier for a Two-Way
Paging Receiver
M.Sc. Advisor Design of a 1-V Full CMOS Opamp
M.Sc. Advisor
Design and Simulation of A GMSK Demodulator
Based on ADPLL
M.Sc. Advisor Design of a Low-Power and High-Speed RISC DSP
M.Sc. Advisor
Optimization and Hardware Modeling of an Standard
ADSL DMT Engine for ASIC Implementation
12 Javad Hadi M.Sc. Advisor Fully Digital Base-Band Pager Demodulator
11
Reza Tusi M.Sc. Advisor
10 Ali Azar
Payvand
9 Mohammad Haji
Rostam
8 Afshin Haft
Baradaran
7 Mehran
Nadjarbashi
6 Sayed
Mohammad-
Reza
Mirzababaei
M.Sc.
Coadvisor
M.Sc. Advisor
M.Sc.
Coadvisor
M.Sc. Advisor
Design, Simulation & Implementation of the Base-
Band Part for a Paging System, Based on ERMES
Standard
ERMES Design and Implementation of an Integrated
Circuit for Paging Applications
System Design of an ADSL Modem and Introduction
of a new Synchronization Method
Design and System Simulation of an ADSL Modem
and Design of Its Equalizer for Integrated Circuits
On routing structure for the hybrid field
programmable architecture
M.Sc. Advisor Web-Server Based Distributed Parallel Processing
5 Saeed Safari M.Sc. Advisor Design of a Programmable Viterbi Encoder/Decoder
4
S. A. Khodaian M.Sc.
3 Behnam Sajadi
Biria
Coadvisor
M.Sc. Advisor
Implementation and Optimization of Turbo-code
Algorithms
Generalization-Improvement Techniques in Neural
Networks
2 Atid Shamaie M.Sc. Advisor Parallel Algorithms for Ellipse Detection in Industrial
Environments
1 Farshad
Baharvand
M.Sc. Advisor
A reduced lookup table for SRAM-based FPGA logic
blocks