Tune that dial - Index of

TECHNOLOGY READER CIRCUITS
ured as an input, which also means that
an internal pull-up resistor is connected
to the pin. The capacitor is charged via
this resistor, but the charging time constant
is much longer than the processor
speed. During the interval when the
input is still low, the value of the key is
changed in rapid succession by a certain
algorithm. This continues until the
capacitor is fully charged. The input
read as a ‘1’ at this point, at which time
the key value stops changing. This
results in a key with a random value.
The randomness arises from the fact
that the charging process is slow relative
to the processor speed. The charging
time corresponds to approximately
10,000 processor cycles. Tests have
shown that the charging time is not
entirely constant. A 0.01-percent
change in the charging time is sufficient
to yield a different result. This
also shows that two different transmitters
will never generate the same key,
especially because most capacitors
have a tolerance of around 5%.
With a normal start-up process
(switching on power), the transmitter
first reads the key present in memory,
but it cannot be transmitted just like
that. A preamble with a duty cycle of
exactly 50% is transmitted first to allow
the operating point of the data slicer to
be adjusted. The transitions in the preamble
also serve to synchronise the
timing at the receiver end with the timing
at the transmitter end. A start bit
is transmitted after the preamble to
indicate that the key will be transmitted
next. The ‘real’ data is only sent
after the start bit, after which the
transmitter is switched off immediately
and the microcontroller enters the
power-down mode to minimise battery
consumption.
A different program is naturally necessary
at the receiver end. In contrast to
the transmitter, the receiver is always
on. In this case the microcontroller listens
to see whether anything is being
received. If it is, it checks whether the
received data stream has the correct
format, which includes checking
whether the start bit synchronisation
is valid. After this it reads the key and
compares it with the value of the key
stored in its EEPROM memory.
The microcontroller has a jumper that
enables it to read the key. If the jumper
is fitted, the receiver is in ‘learn mode’.
If a key is received in this mode, it is
stored in the EEPROM. This means
that the first time the receiver is
switched on, the jumper must be fitted
40
and the code transmitted using the key
transmitter so the key can be stored in
the receiver’s memory. After the
jumper is removed, the receiver should
switch its outputs when the key transmitter
is activated. It may be necessary
to disconnect the receiver
antenna for this procedure and activate
the transmitter close to the receiver.
This will reduce the effect of any interference
signals present at 433.92 MHz.
The watchdog timer is also enabled in
the microcontroller on the receiver end.
If the program counter is affected by a
noise pulse on the supply line, for
instance, which can lead to a ‘hung’
system, the microcontroller will be
reset automatically after approximately
1 second and the receiver will execute
a normal start-up.
Data slicer and Manchester coding
The data slicer in the receiver is built
around an opamp in the receiver IC
that is intended to be used for this purpose.
A data slicer is simply a comparator
with a reference level that is automatically
set when a data signal with
a duty cycle of 50% is received. It is
thus important that the duty cycle of
the data signal is in fact 50%. Manchester
coding is used to achieve this result.
The circuit of the data slicer is shown
in Figure 3. The time constant of R
and C is large relative to the data bit
rate that is used. As a result, the DC
level at the inverting input is equal to
the average value of the received signal.
With a 50% duty cycle, it will thus
be exactly halfway between the minimum
and maximum values. However,
a certain amount of hysteresis is desirable
because the receiver also generates
noise when no signal is present or
the signal is relatively weak. This is
provided by Rl and R2.
It is also necessary to have the transmitter
send a preamble before the
actual data. The preamble consists of
a series of clock pulses with a duty
cycle of 50% and a period that is much
shorter than the RC time constant of
the data slicer. This ensures that the
operating point of the data slicer is set
properly. Manchester coding must be
used to achieve the required 50% duty
cycle with the signal used here. This
essentially amounts to EXORing the
data with a clock signal having the
same period as the bit interval.
The original bit stream is then recovered
in the same manner by EXORing
RSSI
R1
R
C
the received data with a clock signal.
A drawback of Manchester coding is
that it increases the bandwidth of the
transmitted signal by a factor of 2, but
this is not a problem with the low bit
rate used here.
In theory, the bytes output by the
decoding logic when the clock is high
are the same as the bytes output by
the decoding logic when the clock is
low. Both bytes are in fact decoded by
the receiver software. The second byte
should essentially be a copy of the first
one. The correctness of the timing is
monitored closely by comparing the
two bytes after each set of eight
decoded bits.
Timing
The most important aspect with regard
to the algorithms used in the software
at both ends (transmitter and receiver)
is proper timing. The transmitter must
generate a bit stream with a certain
frequency, and the receiver must be
able to recover it with sufficient accuracy.
For this reason, the key transmitter
sends the receiver a preamble consisting
of clock pulses at the same frequency
as the bit rate before it sends
the coded 24-bit key. The preamble is
followed by a start bit that enables the
receiver to deduce that the preamble is
finished and the actual data will follow.
The ATtiny15L microcontrollers at each
end run on their internal RC clocks. A
calibration byte for the clock generator is
programmed into each microcontroller
by the manufacturer. However, this calibration
value is intended to be used
with a supply voltage of 5 V. As the
transmitter operates at 3 V, its clock frequency
is lower than it would be at 5 V.
For this reason, an extra provision has
been made in the software of the
receiver. With the receiver in learn mode
(as described below), the receiver
R2
050364 - 13
DATA OUT
Figure 3. Design of the data slicer in the
MAX1473.
elektor electronics - 12/2006