第44 期: 面向未来十年的“All Programmable” - Xilinx

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手把手课堂 : F P G A 1 0 1 图 1 - 使用 CORE Generator 可以轻松实现众多常见的 CORDIC 配置的 VHDL 代码,如下面的圆函数设计示例。 LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.numeric_std.all; ENTITY synth_cordic IS PORT( clk : IN std_logic; resetn : IN std_logic; z_ip : IN std_logic_vector(16 DOWNTO 0); --1,16 x_ip : IN std_logic_vector(16 DOWNTO 0); --1,16 y_ip : IN std_logic_vector(16 DOWNTO 0); --1,16 cos_op : OUT std_logic_vector(16 DOWNTO 0); --1,16 sin_op : OUT std_logic_vector(16 DOWNTO 0)); --1,16 END ENTITY synth_cordic; ARCHITECTURE rtl OF synth_cordic IS TYPE signed_array IS ARRAY (natural RANGE ) OF signed(17 DOWNTO 0); --ARCTAN Array format 1,16 in radians CONSTANT tan_array : signed_array(0 TO 16) := (to_signed(51471,18), to_signed(30385,18), to_signed(16054,18),to_signed(8149,18), to_signed(4090,18), to_signed(2047,18), to_signed(1023,18), to_signed(511,18), to_signed(255,18), to_signed(127,18), to_signed(63,18), to_signed(31,18), to_signed(15,18), to_signed(7,18),to_signed(3,18), to_signed(1,18), to_signed(0, 18)); SIGNAL x_array : signed_array(0 TO 14) := (OTHERS => (OTHERS =>'0')); SIGNAL y_array : signed_array(0 TO 14) := (OTHERS => (OTHERS =>'0')); SIGNAL z_array : signed_array(0 TO 14) := (OTHERS => (OTHERS =>'0')); BEGIN --convert inputs into signed format PROCESS(resetn, clk) BEGIN IF resetn = '0' THEN x_array (OTHERS => '0')); z_array (OTHERS => '0')); y_array (OTHERS => '0')); ELSIF rising_edge(clk) THEN IF signed(z_ip)< to_signed(0,18) THEN x_array(x_array'low)
tan_array(i); ELSE x_array(i)
Page 1: 赛灵思第四十四期 2 0
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Page 7 and 8: 的三倍,并支持“快速”模
Page 9 and 10: HLS(高层次综合)技术,这是
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Page 13 and 14: 必须尝试各种指令,通过试
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Page 38 and 39: 专家园地 PR_MODULE 发视
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第44 期: 面向未来十年的“All Programmable” - Xilinx

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