VHDL-Grundlagen - Technische Informatik an der Universität Frankfurt

KAPITEL 2. GRUNDLAGEN 9
in0 , in1 : in STD LOGIC ;
out0 : out STD LOGIC
) ;
end component ;
component I n v e r t e r
port (
in0 : in STD LOGIC ;
out0 : out STD LOGIC
) ;
end component ;
signal And out0 , I n v e r t e r 1 o u t 0 : STD LOGIC ;
begin
And : And gatter port map ( a , b , And out0 ) ;
I n v e r t e r 1 : I n v e r t e r port map ( And out0 , I n v e r t e r 1 o u t 0 ) ;
−− S i g n a l mapping
c