Formal Semantics and Analysis of Behavioral AADL Models in ... - IfI
Formal Semantics and Analysis of Behavioral AADL Models in ... - IfI
Formal Semantics and Analysis of Behavioral AADL Models in ... - IfI
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<strong>Formal</strong> <strong>Semantics</strong> <strong>and</strong> <strong>Analysis</strong> <strong>of</strong> <strong>Behavioral</strong><br />
<strong>AADL</strong> <strong>Models</strong> <strong>in</strong> Real-Time Maude<br />
Peter Csaba Ölveczky1 , Artur Boronat 2 , José Meseguer 3 , <strong>and</strong> Edgar Pek 3<br />
1 University <strong>of</strong> Oslo<br />
2 University <strong>of</strong> Leicester<br />
3 University <strong>of</strong> Ill<strong>in</strong>ois at Urbana-Champaign<br />
Abstract. <strong>AADL</strong> is a st<strong>and</strong>ard for model<strong>in</strong>g embedded systems that is<br />
widely used <strong>in</strong> avionics <strong>and</strong> other safety-critical applications. However,<br />
the <strong>AADL</strong> st<strong>and</strong>ard lacks at present a formal semantics, <strong>and</strong> this severely<br />
limits both unambiguous communication among model developers, <strong>and</strong><br />
the development <strong>of</strong> simulators <strong>and</strong> formal analysis tools. In this work we<br />
present a formal real-time rewrit<strong>in</strong>g logic semantics for a behavioral subset<br />
<strong>of</strong> <strong>AADL</strong> which <strong>in</strong>cludes the essential aspects <strong>of</strong> its behavior annex.<br />
Our semantics is directly executable <strong>in</strong> Real-Time Maude <strong>and</strong> provides<br />
an <strong>AADL</strong> simulator <strong>and</strong> LTL model check<strong>in</strong>g tool called <strong>AADL</strong>2Maude.<br />
<strong>AADL</strong>2Maude is <strong>in</strong>tegrated with OSATE, so that OSATE’s code generation<br />
facility is used to automatically transform <strong>AADL</strong> models <strong>in</strong>to<br />
their correspond<strong>in</strong>g Real-Time Maude specifications. Such transformed<br />
models can then be executed <strong>and</strong> model checked by Real-Time Maude.<br />
We present our semantics, <strong>and</strong> two case studies <strong>in</strong> which safety-critical<br />
properties are verified <strong>in</strong> <strong>AADL</strong>2Maude.<br />
1 Introduction<br />
<strong>AADL</strong> [15] is both a model<strong>in</strong>g language for real-time embedded systems <strong>and</strong> an<br />
<strong>in</strong>ternational st<strong>and</strong>ard widely used <strong>in</strong> <strong>in</strong>dustry. It has good features to model the<br />
real-time aspects <strong>of</strong> embedded systems <strong>and</strong> to represent both the s<strong>of</strong>tware <strong>and</strong><br />
hardware architectures <strong>of</strong> the components mak<strong>in</strong>g up such systems. It does however<br />
lack at present a formal semantics. This lack is particularly important for<br />
real-time embedded systems, because many <strong>of</strong> them —<strong>in</strong> areas such as avionics,<br />
motor vehicles, <strong>and</strong> medical systems— are safety-critical systems, whose failures<br />
may cause great damage to persons <strong>and</strong>/or valuable assets. Indeed such systems<br />
are <strong>of</strong>ten required to pass str<strong>in</strong>gent processes <strong>of</strong> certification to provide sufficiently<br />
strong evidence about their safety. Furthermore, <strong>AADL</strong> models are not<br />
executable, which limits not just the possibility <strong>of</strong> formal analysis <strong>of</strong> their safety<br />
<strong>and</strong> liveness properties, but even the possibility <strong>of</strong> simulat<strong>in</strong>g them.<br />
It seems clear that overcom<strong>in</strong>g these limitations <strong>of</strong> <strong>AADL</strong> is highly desirable,<br />
but requires <strong>in</strong> an essential way the use <strong>of</strong> formal methods, because <strong>in</strong> the absence<br />
<strong>of</strong> a precise mathematical semantics any pretense <strong>of</strong> achiev<strong>in</strong>g formal verification<br />
is mean<strong>in</strong>gless. Furthermore, these formal methods should be supported by tools<br />
that are <strong>in</strong>tegrated <strong>in</strong>to the <strong>AADL</strong> tool cha<strong>in</strong>. A further, highly desirable goal
2<br />
is to have a formal semantics <strong>of</strong> <strong>AADL</strong> that can be used to automatically generate<br />
formal executable specifications <strong>of</strong> <strong>AADL</strong> models, s<strong>in</strong>ce the first <strong>and</strong> most<br />
basic way <strong>of</strong> analyz<strong>in</strong>g <strong>AADL</strong> models should be the capacity to simulate such<br />
models; <strong>and</strong> s<strong>in</strong>ce such formal executable specifications can then also be used<br />
for automatic verification <strong>of</strong> safety <strong>and</strong> liveness properties by model check<strong>in</strong>g.<br />
There isn’t <strong>of</strong> course a s<strong>in</strong>gle choice <strong>of</strong> a formal framework <strong>in</strong> which to first<br />
def<strong>in</strong>e a formal semantics for <strong>AADL</strong> <strong>and</strong> then support both simulation <strong>and</strong><br />
formal analysis <strong>of</strong> <strong>AADL</strong> models. What we have is a spectrum <strong>of</strong> choices, each<br />
with its specific advantages <strong>and</strong> its possible limitations. This technical report<br />
describes our experience <strong>in</strong> def<strong>in</strong><strong>in</strong>g a formal semantics for a substantial subset<br />
<strong>of</strong> <strong>AADL</strong> <strong>in</strong> the Real-Time Maude formal specification language [14]; <strong>and</strong> <strong>in</strong><br />
directly us<strong>in</strong>g such a formal semantics to simulate <strong>and</strong> formally analyze <strong>AADL</strong><br />
models. We have found the rewrit<strong>in</strong>g logic formal framework supported by Real-<br />
Time Maude particularly well suited for this task for the follow<strong>in</strong>g reasons:<br />
– Real-time formalism. All real-time aspects <strong>of</strong> <strong>AADL</strong> can be directly <strong>and</strong><br />
naturally formally modeled by means <strong>of</strong> real-time rewrite theories.<br />
– Support for nested objects. <strong>AADL</strong> models are structured <strong>in</strong> nested hierarchies<br />
<strong>of</strong> components. Much would be lost <strong>in</strong> translation if such structure were not<br />
preserved. Real-Time Maude’s support for object classes with a “Russian<br />
dolls” nested structure (see [10]) provides an essentially isomorphic formal<br />
counterpart for an <strong>AADL</strong> model. This is important to achieve a small representational<br />
distance between an <strong>AADL</strong> model <strong>and</strong> its correspond<strong>in</strong>g formal<br />
specification, <strong>and</strong> to be able to map back simulation <strong>and</strong> formal analysis<br />
results from the formal specification to the orig<strong>in</strong>al model for diagnostic<br />
purposes.<br />
– Wide range <strong>of</strong> formal analysis capabilities. By automat<strong>in</strong>g the <strong>AADL</strong> formal<br />
semantics with the <strong>AADL</strong>2Maude tool, one can automatically generate<br />
formal executable specifications <strong>of</strong> <strong>AADL</strong> models <strong>in</strong> Real-Time Maude for<br />
simulation, reachability analysis, <strong>and</strong> LTL model check<strong>in</strong>g purposes.<br />
One potential limitation <strong>of</strong> the Real-Time Maude framework is that, because <strong>of</strong><br />
its flexibility to represent many communication models, object architectures, <strong>and</strong><br />
unbounded algebraic data structures, <strong>in</strong> general its specifications fall outside the<br />
automata-theoretic decidable fragments for real-time model check<strong>in</strong>g. However,<br />
because <strong>of</strong> the rout<strong>in</strong>e use <strong>of</strong> nested object hierarchies <strong>and</strong> <strong>of</strong> different data<br />
structures <strong>in</strong> <strong>AADL</strong> itself, plus the need for formal properties <strong>in</strong>volv<strong>in</strong>g such<br />
structures, we doubt that <strong>AADL</strong> models can be faithfully modeled <strong>in</strong> automatabased<br />
formalisms, although it may be possible to model abstractions <strong>of</strong> such<br />
models for restricted subsets <strong>of</strong> <strong>AADL</strong>. Furthermore, the lack <strong>of</strong> decidability<br />
for general Real-Time Maude models is substantially compensated for by the<br />
decidability <strong>of</strong> time-bounded LTL properties for a wide class <strong>of</strong> models, <strong>in</strong>clud<strong>in</strong>g<br />
a large class <strong>of</strong> object-oriented systems, under mild checkable conditions [13].<br />
Our Contribution. Our ma<strong>in</strong> contributions are: (i) a formal semantics for a<br />
substantial subset <strong>of</strong> <strong>AADL</strong>, <strong>in</strong>clud<strong>in</strong>g the most essential aspects <strong>of</strong> <strong>AADL</strong>’s<br />
behavior annex; (ii) the <strong>AADL</strong>2Maude tool, automat<strong>in</strong>g the generation <strong>of</strong> Real-
Time Maude specifications for <strong>AADL</strong> models <strong>in</strong> OSATE based on such a semantics<br />
<strong>and</strong> support<strong>in</strong>g simulation, reachability <strong>and</strong> LTL model check<strong>in</strong>g analyses;<br />
<strong>and</strong> (iii) two case studies, one on safe <strong>in</strong>teroperation <strong>of</strong> medical devices <strong>and</strong> one<br />
on the safety <strong>of</strong> avionics systems, demonstrat<strong>in</strong>g the usefulness <strong>of</strong> this semantics<br />
<strong>and</strong> tools <strong>in</strong> concrete examples. This work should be seen <strong>in</strong> the context <strong>of</strong> other<br />
recent approaches to the formal analysis <strong>of</strong> <strong>AADL</strong> models [2, 7, 1, 18, 17], which<br />
are further discussed <strong>in</strong> Section 5. To the best <strong>of</strong> our knowledge, our approach<br />
is the only one to date to provide an <strong>in</strong>tuitive semantics, preserv<strong>in</strong>g the components’<br />
hierarchical structure, <strong>and</strong> also simulation <strong>and</strong> LTL model check<strong>in</strong>g<br />
capabilities for <strong>AADL</strong> behavioral models <strong>in</strong> its behavior annex, as opposed to<br />
approaches that specify <strong>AADL</strong> model behavior <strong>in</strong> formalisms external to <strong>AADL</strong>.<br />
The paper is organized as follows. Section 2 gives a brief <strong>in</strong>troduction to<br />
<strong>AADL</strong> <strong>and</strong> Real-Time Maude. Section 3 presents the Real-Time Maude semantics<br />
<strong>of</strong> a behavioral subset <strong>of</strong> <strong>AADL</strong>, <strong>and</strong> shows how <strong>AADL</strong> models can be<br />
formally analyzed <strong>in</strong> <strong>AADL</strong>2Maude. Section 4 reports on the verification <strong>of</strong> the<br />
avionics active st<strong>and</strong>by example. Section 5 discusses related work on formaliz<strong>in</strong>g<br />
fragments <strong>of</strong> <strong>AADL</strong>, <strong>and</strong> Section 6 gives some conclud<strong>in</strong>g remarks.<br />
Acknowledgments. Xiaokang Qiu contributed to an earlier version <strong>of</strong> this<br />
technical report, <strong>and</strong> also to earlier prototype versions <strong>of</strong> the <strong>AADL</strong> semantics<br />
<strong>and</strong> the verification <strong>of</strong> the avionics case study. This work reported here is part <strong>of</strong><br />
a Rockwell-Coll<strong>in</strong>s sponsored jo<strong>in</strong>t project with Pr<strong>of</strong>. Lui Sha <strong>and</strong> his students<br />
at UIUC <strong>and</strong> reseachers at Rockwell-Coll<strong>in</strong>s. We have benefitted very much<br />
form Pr<strong>of</strong>. Sha’s comments <strong>and</strong> suggestions dur<strong>in</strong>g many project meet<strong>in</strong>gs, <strong>and</strong><br />
also from the help <strong>and</strong> suggestions <strong>of</strong> other members <strong>of</strong> the jo<strong>in</strong>t work<strong>in</strong>g group,<br />
particularly from Joe Hendrix (who made some <strong>in</strong>itial contributions to the <strong>AADL</strong><br />
to Maude translation ideas), Tanya Crenshaw, who was an early user <strong>of</strong> Real-<br />
Time Maude for analysis <strong>of</strong> embedded systems, Mu Sun who pioneered the static<br />
analysis <strong>of</strong> <strong>AADL</strong> models <strong>in</strong> Maude us<strong>in</strong>g MOMENT2, <strong>and</strong> Abdullah Al-Nayeem<br />
<strong>and</strong> M<strong>in</strong>-Young Nam, who have helped us greatly with <strong>AADL</strong> expertise <strong>and</strong> with<br />
concrete <strong>AADL</strong> examples as those mentioned <strong>in</strong> this report. We are also very<br />
grateful to Steve Miller <strong>and</strong> Darren C<strong>of</strong>er from Rockwell-Coll<strong>in</strong>s for many helpful<br />
suggestions on this work along our regular project meet<strong>in</strong>gs.<br />
2 Prelim<strong>in</strong>aries on <strong>AADL</strong> <strong>and</strong> Real-Time Maude<br />
2.1 <strong>AADL</strong><br />
The SEA Architecture <strong>Analysis</strong> & Design Language (<strong>AADL</strong>) [15, 16] is an <strong>in</strong>dustrial<br />
st<strong>and</strong>ard used <strong>in</strong> avionics, aerospace, automotive, <strong>and</strong> robotics communities<br />
to describe a performance-critical embedded real-time system as an assembly <strong>of</strong><br />
s<strong>of</strong>tware components mapped onto an execution platform.<br />
An <strong>AADL</strong> model describes a system as a hierarchy <strong>of</strong> hardware <strong>and</strong> s<strong>of</strong>tware<br />
components. A component is def<strong>in</strong>ed by its name, its <strong>in</strong>terface consist<strong>in</strong>g<br />
<strong>of</strong> <strong>in</strong>put <strong>and</strong> output ports, its subcomponents <strong>and</strong> their <strong>in</strong>teraction, <strong>and</strong> other<br />
type-specific properties. System components are the top-level components, <strong>and</strong><br />
3
4<br />
can consist <strong>of</strong> other system components as well as <strong>of</strong> hardware <strong>and</strong> s<strong>of</strong>tware<br />
components. Hardware components <strong>in</strong>clude: processor components that schedule<br />
<strong>and</strong> execute threads; memory components; device components represent<strong>in</strong>g<br />
devices like sensors <strong>and</strong> actuators that <strong>in</strong>terface with the environment; <strong>and</strong> bus<br />
components that <strong>in</strong>terconnect processors, memory, <strong>and</strong> devices. S<strong>of</strong>tware components<br />
<strong>in</strong>clude: thread components model<strong>in</strong>g the application s<strong>of</strong>tware to be<br />
executed; process components def<strong>in</strong><strong>in</strong>g protected memory that can be accessed<br />
by its thread subcomponents; <strong>and</strong> data components represent<strong>in</strong>g data types. In<br />
<strong>AADL</strong>, thread behavior is typically described us<strong>in</strong>g <strong>AADL</strong>’s behavior annex [5],<br />
which models programs as transition systems with local state variables.<br />
An <strong>AADL</strong> model specifies how the different components <strong>in</strong>teract <strong>and</strong> are<br />
<strong>in</strong>tegrated to form a complete system. The <strong>AADL</strong> st<strong>and</strong>ard also describes the<br />
runtime mechanisms for h<strong>and</strong>l<strong>in</strong>g message <strong>and</strong> event pass<strong>in</strong>g, synchronized access<br />
to shared resources, thread schedul<strong>in</strong>g when several threads run on the same<br />
processor, <strong>and</strong> dynamic reconfiguration that are specified by mode transitions.<br />
<strong>AADL</strong> has a MOF meta-model, <strong>and</strong> the OSATE model<strong>in</strong>g environment provides<br />
a set <strong>of</strong> plug-<strong>in</strong>s for front-end process<strong>in</strong>g <strong>of</strong> <strong>AADL</strong> models on top <strong>of</strong> the<br />
Eclipse platform.<br />
2.2 Rewrit<strong>in</strong>g Logic, Maude, <strong>and</strong> Real-Time Maude<br />
Rewrit<strong>in</strong>g Logic <strong>and</strong> Maude. A Maude [4] module specifies a rewrite theory<br />
<strong>of</strong> the form (Σ, E ∪A, R), where (Σ, E ∪A) is a theory <strong>in</strong> membership equational<br />
logic [8], with Σ a signature, E a set <strong>of</strong> conditional equations <strong>and</strong> memberships,<br />
<strong>and</strong> A a set <strong>of</strong> equational axioms such as associativity, commutativity,<br />
<strong>and</strong> identity, so that equational deduction is performed modulo the axioms A.<br />
The theory (Σ, E ∪ A) specifies the system’s state space as an algebraic data<br />
type. R is a collection <strong>of</strong> labeled conditional rewrite rules specify<strong>in</strong>g the system’s<br />
local transitions, each <strong>of</strong> which has the form<br />
[l] : t −→ t ′ if<br />
n<br />
m<br />
ui −→ vi ∧ wj = w ′ j,<br />
i=1<br />
where l is a label. Intuitively, such a rule specifies a one-step transition from<br />
a substitution <strong>in</strong>stance <strong>of</strong> t to the correspond<strong>in</strong>g substitution <strong>in</strong>stance <strong>of</strong> t ′ ,<br />
provided the condition holds. The rules are implicitly universally quantified by<br />
the variables appear<strong>in</strong>g <strong>in</strong> the Σ-terms t, t ′ , ui, vi, wj, <strong>and</strong> w ′ j . The rules are<br />
applied modulo the equations E ∪ A. 4<br />
We briefly summarize the syntax <strong>of</strong> Maude. Operators are <strong>in</strong>troduced with<br />
the op keyword. They can have user-def<strong>in</strong>able syntax, with underbars ‘_’ mark<strong>in</strong>g<br />
the argument positions, <strong>and</strong> are declared with the sorts <strong>of</strong> their arguments<br />
<strong>and</strong> the sort <strong>of</strong> their result. Some operators can have equational attributes, such<br />
as assoc, comm, <strong>and</strong> id, stat<strong>in</strong>g, for example, that the operator is associative<br />
4 Operationally, a term is reduced to its E-normal form modulo A before any rewrite<br />
rule <strong>in</strong> R is applied <strong>in</strong> Maude.<br />
j=1
<strong>and</strong> commutative <strong>and</strong> has a certa<strong>in</strong> identity element. Such attributes are then<br />
used by the Maude eng<strong>in</strong>e to match terms modulo the declared axioms. There<br />
are three k<strong>in</strong>ds <strong>of</strong> logical statements, namely, equations—<strong>in</strong>troduced with the<br />
keywords eq, or, for conditional equations, ceq—memberships—declar<strong>in</strong>g that<br />
a term has a certa<strong>in</strong> sort <strong>and</strong> <strong>in</strong>troduced with the keywords mb <strong>and</strong> cmb—<strong>and</strong><br />
rewrite rules—<strong>in</strong>troduced with the keywords rl <strong>and</strong> crl. The mathematical variables<br />
<strong>in</strong> such statements are declared with the keywords var <strong>and</strong> vars. An equation<br />
f(t1, . . . , tn) = t with the owise (for “otherwise”) attribute can be applied<br />
to a subterm f(. . .) only if no other equation with left-h<strong>and</strong> side f(u1, . . . , un)<br />
can be applied. 5<br />
In object-oriented Maude modules one can declare classes <strong>and</strong> subclasses. A<br />
class declaration<br />
class C | att1 : s1, ... , attn : sn .<br />
declares an object class C with attributes att1 to attn <strong>of</strong> sorts s1 to sn. An object<br />
<strong>of</strong> class C <strong>in</strong> a given state is represented as a term<br />
< O : C | att1 : val1, ..., attn : valn ><br />
where O is the object’s name, <strong>and</strong> where val1 to valn are the current values<br />
<strong>of</strong> the attributes att1 to attn. In an object-oriented system, the state, which<br />
is usually called a configuration, is a term <strong>of</strong> the built-<strong>in</strong> sort Configuration.<br />
It has typically the structure <strong>of</strong> a multiset made up <strong>of</strong> objects <strong>and</strong> messages.<br />
Multiset union for configurations is denoted by a juxtaposition operator (empty<br />
syntax) that is declared associative <strong>and</strong> commutative <strong>and</strong> hav<strong>in</strong>g the none multiset<br />
as its identity element, so that order <strong>and</strong> parentheses do not matter, <strong>and</strong> so<br />
that rewrit<strong>in</strong>g is multiset rewrit<strong>in</strong>g supported directly <strong>in</strong> Maude. The dynamic<br />
behavior <strong>of</strong> concurrent object systems is axiomatized by specify<strong>in</strong>g each <strong>of</strong> its<br />
concurrent transition patterns by a rewrite rule. For example, the rule<br />
rl [l] : < O : C | a1 : 0, a2 : y, a3 : w, a4 : z > =><br />
< O : C | a1 : T, a2 : y, a3 : y + w, a4 : z ><br />
def<strong>in</strong>es a parameterized family <strong>of</strong> transitions (one for each substitution <strong>in</strong>stance)<br />
which can be applied whenever the attribute a1 <strong>of</strong> an object O <strong>of</strong> class C has<br />
the value 0, with the effect <strong>of</strong> alter<strong>in</strong>g the attributes a1 <strong>and</strong> a3 <strong>of</strong> the object.<br />
“Irrelevant” attributes (such as a4, <strong>and</strong> the right-h<strong>and</strong> side occurrence <strong>of</strong> a2)<br />
need not be mentioned <strong>in</strong> a rule.<br />
A subclass <strong>in</strong>herits all the attributes <strong>and</strong> rules <strong>of</strong> its superclasses.<br />
Object-Oriented Specification <strong>in</strong> Real-Time Maude. Real-Time Maude [14]<br />
is a high-performance tool that extends Maude to support the formal specification<br />
<strong>and</strong> analysis <strong>of</strong> object-based real-time systems. A Real-Time Maude<br />
timed module specifies a real-time rewrite theory [12], that is, a rewrite theory<br />
R = (Σ, E ∪ A, R), such that:<br />
5 A specification with owise equations can be transformed to an equivalent system<br />
without such equations [4].<br />
5
6<br />
1. (Σ, E ∪ A) conta<strong>in</strong>s a specification <strong>of</strong> a sort Time which def<strong>in</strong>es the time<br />
doma<strong>in</strong> (which may be discrete or dense). Although a timed module is<br />
parametric on the time doma<strong>in</strong>, Real-Time Maude provides some predef<strong>in</strong>ed<br />
modules specify<strong>in</strong>g useful time doma<strong>in</strong>s. For example, the modules<br />
NAT-TIME-DOMAIN-WITH-INF <strong>and</strong> POSRAT-TIME-DOMAIN-WITH-INF def<strong>in</strong>e the<br />
time doma<strong>in</strong> to be, respectively, the natural numbers <strong>and</strong> the nonnegative<br />
rational numbers.<br />
2. The rules <strong>in</strong> R are decomposed <strong>in</strong>to:<br />
– “ord<strong>in</strong>ary” rewrite rules that model <strong>in</strong>stantaneous change, <strong>and</strong><br />
– tick (rewrite) rules that model the elapse <strong>of</strong> time <strong>in</strong> a system. Such tick<br />
rules have the form<br />
crl [l] : {t} => {t ′ } <strong>in</strong> time u if cond .<br />
where t <strong>and</strong> t ′ are terms <strong>of</strong> sort Configuration, { } is a built-<strong>in</strong> constructor<br />
<strong>of</strong> a new sort GlobalSystem, <strong>and</strong> where u is a term <strong>of</strong> sort Time<br />
denot<strong>in</strong>g the duration <strong>of</strong> the rewrite.<br />
The <strong>in</strong>itial state <strong>of</strong> a real-time system so specified must be reducible to a<br />
ground term {t0} us<strong>in</strong>g the equations <strong>in</strong> the specification. The form <strong>of</strong> the tick<br />
rules then ensures uniform time elapse <strong>in</strong> all parts <strong>of</strong> a system.<br />
<strong>Formal</strong> <strong>Analysis</strong> <strong>in</strong> Real-Time Maude. Timed modules are executable under<br />
reasonable assumptions, <strong>and</strong> Real-Time Maude provides a spectrum <strong>of</strong> formal<br />
analysis capabilities.<br />
Real-Time Maude’s timed “fair” rewrite comm<strong>and</strong> simulates one behavior<br />
<strong>of</strong> the system up to a certa<strong>in</strong> duration. It is written with syntax<br />
(tfrew t <strong>in</strong> time * pattern such that cond <strong>in</strong> time
for b a term <strong>of</strong> sort Bool, which def<strong>in</strong>es the state proposition prop to hold <strong>in</strong><br />
all states {t} where {t} |= prop evaluates to true. A temporal logic formula<br />
is constructed by state propositions <strong>and</strong> temporal logic operators such as True,<br />
False, ~ (negation), /\, \/, -> (implication), [] (“always”), (“eventually”),<br />
O (“next”), <strong>and</strong> U (“until”). The model check<strong>in</strong>g comm<strong>and</strong> has syntax<br />
(mc t |=u formula .)<br />
for t the <strong>in</strong>itial state <strong>and</strong> formula the temporal logic formula.<br />
3 Real-Time Maude <strong>Semantics</strong> for a <strong>Behavioral</strong> Subset <strong>of</strong><br />
<strong>AADL</strong><br />
This section presents the Real-Time Maude semantics for a behavioral subset <strong>of</strong><br />
<strong>AADL</strong>. Section 3.1 presents the chosen subset <strong>of</strong> <strong>AADL</strong>, Section 3.2 presents its<br />
Real-Time Maude semantics, <strong>and</strong> Section 3.3 expla<strong>in</strong>s how <strong>AADL</strong> models can<br />
be formally analyzed <strong>in</strong> Real-Time Maude.<br />
3.1 Overview <strong>of</strong> a <strong>Behavioral</strong> Subset <strong>of</strong> <strong>AADL</strong><br />
This section gives an overview <strong>of</strong> the subset <strong>of</strong> <strong>AADL</strong> for which we have def<strong>in</strong>ed<br />
a rewrit<strong>in</strong>g logic semantics.<br />
Components. In <strong>AADL</strong>, a system is modeled as a collection <strong>of</strong> s<strong>of</strong>tware <strong>and</strong><br />
hardware components. S<strong>in</strong>ce we have focused on the s<strong>of</strong>tware parts <strong>of</strong> <strong>AADL</strong>,<br />
the follow<strong>in</strong>g description only deals with the s<strong>of</strong>tware components <strong>and</strong> features.<br />
A component is given by its type <strong>and</strong> its implementation. A component type<br />
specifies the component’s <strong>in</strong>terface <strong>in</strong> terms <strong>of</strong> features <strong>and</strong> properties. In the<br />
s<strong>of</strong>tware portion, features are just <strong>in</strong>put <strong>and</strong> output ports. Properties support<br />
specialized model<strong>in</strong>g <strong>and</strong> analysis capabilities that can be def<strong>in</strong>ed <strong>in</strong> <strong>AADL</strong><br />
annexes. A component implementation specifies the <strong>in</strong>ternal structure <strong>of</strong> the<br />
component <strong>in</strong> terms <strong>of</strong> a set <strong>of</strong> subcomponents, a set <strong>of</strong> connections l<strong>in</strong>k<strong>in</strong>g the<br />
ports <strong>of</strong> the subcomponents, <strong>and</strong> modes that represent operational states <strong>of</strong><br />
components (see below).<br />
System components are the top level s<strong>of</strong>tware components. A process component<br />
conta<strong>in</strong>s a set <strong>of</strong> thread components that together def<strong>in</strong>e the dynamic<br />
behavior <strong>of</strong> the process.<br />
Port Connections. Port connections l<strong>in</strong>k ports to enable the exchange <strong>of</strong> data<br />
<strong>and</strong> events among components. Ports are directional. An out port represents<br />
output provided by the sender, <strong>and</strong> an <strong>in</strong> port represents <strong>in</strong>put needed by the<br />
receiver. A port is either a data port, an event port, or an event data port. Each<br />
port is accessible through its buffer. Buffers <strong>of</strong> event ports <strong>and</strong> event data ports<br />
support queue<strong>in</strong>g <strong>of</strong>, respectively, “events” <strong>and</strong> message data, while buffers <strong>of</strong><br />
data ports only keep the latest data. In addition, each thread port is associated<br />
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to an <strong>in</strong>ternal buffer, which is accessible by the thread. The dequeue protocol<br />
attribute determ<strong>in</strong>es how many elements <strong>in</strong> the port buffer are transferred to<br />
the thread’s <strong>in</strong>ternal buffer when a thread is dispatched.<br />
A level-up connection l<strong>in</strong>ks an outgo<strong>in</strong>g port <strong>in</strong> a subcomponent to an outgo<strong>in</strong>g<br />
port <strong>in</strong> the conta<strong>in</strong><strong>in</strong>g component. A level-down connection l<strong>in</strong>ks an <strong>in</strong>com<strong>in</strong>g<br />
port <strong>of</strong> a component to an <strong>in</strong>com<strong>in</strong>g port <strong>in</strong> one <strong>of</strong> its subcomponents. A samelevel<br />
connection connects an outgo<strong>in</strong>g port <strong>of</strong> a component to <strong>in</strong>com<strong>in</strong>g ports<br />
<strong>of</strong> another component at the same level <strong>in</strong> the conta<strong>in</strong>ment hierarchy. <strong>AADL</strong><br />
supports 1-to-n connectivity for event <strong>and</strong> event data ports at the same level.<br />
Modes. Modes represent the operational states <strong>of</strong> components. A component<br />
can have mode-specific property values, subcomponents, <strong>and</strong> connections. Mode<br />
transitions are triggered by events. In the follow<strong>in</strong>g example, a simplified blood<br />
pressure monitor process has two modes, fast <strong>and</strong> slow. The fast <strong>and</strong> slow<br />
modes have their own implementations, send<strong>in</strong>g out the requestbp signal every<br />
100, respectively 1000, milliseconds. An <strong>in</strong>com<strong>in</strong>g event through the port<br />
modechange results <strong>in</strong> mode switch between slow mode <strong>and</strong> fast mode.<br />
process bpProc<br />
features<br />
modeChange: <strong>in</strong> event port;<br />
requestbp: out event port;<br />
end bpProc;<br />
process implementation bpProc.i<br />
subcomponents<br />
slowTh: thread mcTh.slow <strong>in</strong> modes (slow);<br />
fastTh: thread mcTh.fast <strong>in</strong> modes (fast);<br />
connections<br />
event port slowTh.requestbp -> requestbp <strong>in</strong> modes (slow);<br />
event port fastTh.requestbp -> requestbp <strong>in</strong> modes (fast);<br />
modes<br />
slow: <strong>in</strong>itial mode ;<br />
fast: mode ;<br />
slow -[modeChange]-> fast;<br />
fast -[modeChange]-> slow;<br />
end bpProc.i;<br />
thread mcTh<br />
features<br />
requestbp: out event port;<br />
end mcTh;<br />
thread implementation mcTh.slow<br />
properties<br />
Period => 1000 Ms;<br />
annex Behavior_specification {**<br />
states
send : <strong>in</strong>itial state;<br />
transitions<br />
send -[]-> send {requestbp!};<br />
**};<br />
end mcTh.slow;<br />
thread implementation mcTh.fast<br />
properties<br />
Period => 100 Ms;<br />
annex Behavior_specification {**<br />
states<br />
send : <strong>in</strong>itial state;<br />
transitions<br />
send -[]-> send {requestbp!};<br />
**};<br />
end mcTh.fast;<br />
(We do not support at the moment some other features <strong>of</strong> modes, such as,<br />
e.g., the “applies to” construct, where the properties <strong>of</strong> a subcomponent are<br />
directly modified as a result <strong>of</strong> a mode change <strong>in</strong> one <strong>of</strong> its supercomponents.)<br />
Dispatch Protocols. The dispatch protocol property <strong>of</strong> a thread determ<strong>in</strong>es<br />
when the thread is executed. A periodic thread is activated at time <strong>in</strong>tervals <strong>of</strong><br />
the specified period T ; an aperiodic thread is activated when an event arrives at<br />
a port <strong>of</strong> the thread; a sporadic thread is activated when an event arrives <strong>and</strong><br />
the <strong>in</strong>terval between two dispatches is at least T ; <strong>and</strong> a background thread is<br />
(re-)activated upon the completion <strong>of</strong> execution.<br />
<strong>Behavioral</strong> Annex. The dynamic behavior <strong>of</strong> a thread is def<strong>in</strong>ed <strong>in</strong> <strong>AADL</strong><br />
us<strong>in</strong>g <strong>AADL</strong>’s behavioral annex [5]. Given a f<strong>in</strong>ite set <strong>of</strong> states (or locations),<br />
<strong>and</strong> a set <strong>of</strong> state variables, the dynamic behavior <strong>of</strong> a thread is def<strong>in</strong>ed by a set<br />
<strong>of</strong> guarded state transitions <strong>of</strong> the form<br />
s -[guard]-> s ′ {actions}<br />
where s <strong>and</strong> s ′ are states, <strong>and</strong> where the guard is a boolean condition on the<br />
values <strong>of</strong> the state variables <strong>and</strong>/or the presence <strong>of</strong> events or data <strong>in</strong> the thread’s<br />
<strong>in</strong>put ports. The actions that are performed when a transition is applied may<br />
update the state variables, generate new output events <strong>and</strong>/or data, <strong>and</strong>/or<br />
suspend the thread for a given amount <strong>of</strong> time. Actions are built from basic<br />
actions us<strong>in</strong>g a small set <strong>of</strong> control structures allow<strong>in</strong>g sequenc<strong>in</strong>g, conditionals,<br />
<strong>and</strong> f<strong>in</strong>ite loops.<br />
When a thread is activated, an enabled transition is nondeterm<strong>in</strong>istically<br />
selected <strong>and</strong> applied; if the result<strong>in</strong>g state s ′ is not a complete state, another<br />
transition is applied, <strong>and</strong> so on, until a complete state is reached (or the thread<br />
is suspended).<br />
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Value Constra<strong>in</strong>ts. In embedded applications, such as the active st<strong>and</strong>by<br />
system discussed <strong>in</strong> Section 4, the environment <strong>in</strong>teract<strong>in</strong>g with sensors <strong>and</strong><br />
actuators can be modeled as a special “environment” component that nondeterm<strong>in</strong>istically<br />
generates events.<br />
Typically, the data/events from the environment are <strong>in</strong>terdependent, so that<br />
not all possible comb<strong>in</strong>ations <strong>of</strong> values are legal <strong>in</strong>puts from the environment.<br />
Us<strong>in</strong>g the fact that we can def<strong>in</strong>e new properties <strong>in</strong> <strong>AADL</strong>, Abdullah Al-Nayeem<br />
has extended <strong>AADL</strong> with a property feature to express such constra<strong>in</strong>ts on a set<br />
<strong>of</strong> values. For example, <strong>in</strong> the avionics example <strong>in</strong> Section 4, the environment<br />
sends five boolean-valued signals <strong>in</strong> each period. One <strong>of</strong> these reports whether<br />
or not side 1 has failed; another signal reports whether side 2 has failed. It is<br />
assumed that both sides cannot fail at the same time. Hence, the <strong>in</strong>put from<br />
the environment <strong>in</strong> each round is a five-tuple (b1, b2, . . . , b5) satisfy<strong>in</strong>g the value<br />
constra<strong>in</strong>t (b1 ∨ b2). See Section 4 for more details.<br />
An <strong>AADL</strong> Example. As a small example <strong>of</strong> an <strong>AADL</strong> specification with<strong>in</strong><br />
our targeted subset <strong>of</strong> <strong>AADL</strong>, consider a system consist<strong>in</strong>g <strong>of</strong> a controller, a<br />
ventilator mach<strong>in</strong>e that assists a patient’s breath<strong>in</strong>g dur<strong>in</strong>g surgery, <strong>and</strong> an Xray<br />
device. Whenever a button is pushed to take an X-ray, <strong>and</strong> the ventilator<br />
mach<strong>in</strong>e has not paused sometime <strong>in</strong> the past 10 m<strong>in</strong>utes, the ventilator mach<strong>in</strong>e<br />
should pause for two seconds, start<strong>in</strong>g one second after the button is pushed,<br />
<strong>and</strong> the X-ray should be taken after two seconds. To execute the system, we also<br />
add a test activator that pushes the button every second.<br />
The follow<strong>in</strong>g <strong>AADL</strong> model was developed by M<strong>in</strong>-Young Nam.<br />
The entire system Wholesys is a closed system that does not have any features<br />
(i.e., ports) to the outside world. Hence, its type (<strong>in</strong>terface) is empty:<br />
system Wholesys<br />
end Wholesys;<br />
The implementation <strong>of</strong> the entire system describes the architecture <strong>of</strong> the system,<br />
with four subcomponents <strong>and</strong> the connections l<strong>in</strong>k<strong>in</strong>g these subcomponents:<br />
system implementation Wholesys.imp<br />
subcomponents<br />
TestActivator: system TA.impl;<br />
XRayMach<strong>in</strong>e: system XM.impl;<br />
VentilatorMach<strong>in</strong>e: system VM.impl;<br />
Controller: system Controller.impl;<br />
connections<br />
C01: event data port Controller.xmContrOutput -><br />
XrayMach<strong>in</strong>e.controllerInput;<br />
C02: event data port Controller.vmContrOutput -><br />
VentilatorMach<strong>in</strong>e.controllerInput;<br />
C03: event data port VentilatorMach<strong>in</strong>e.feedback -> Controller.feedback;<br />
C04: event data port TestActivator.pressEvent -><br />
Controller.comm<strong>and</strong>Input;<br />
end Wholesys.imp;
The test activator TestActivator, whose job it is to generate an event every<br />
second, is an <strong>in</strong>stance <strong>of</strong> a system <strong>of</strong> type TA, hav<strong>in</strong>g as <strong>in</strong>terface the output port<br />
pressEvent:<br />
system TA<br />
features<br />
pressEvent: out event data port Behavior::<strong>in</strong>teger;<br />
end TA;<br />
Its implementation consists <strong>of</strong> a s<strong>in</strong>gle process taPr, which is an <strong>in</strong>stance <strong>of</strong><br />
taProcess.impl:<br />
system implementation TA.impl<br />
subcomponents<br />
taPr: process taProcess.impl;<br />
connections<br />
C90: event data port taPr.pressEvent -> pressEvent;<br />
end TA.impl;<br />
A taProcess.impl itself consists <strong>of</strong> a s<strong>in</strong>gle thread taTh:<br />
process taProcess<br />
features<br />
pressEvent: out event data port Behavior::<strong>in</strong>teger;<br />
end taProcess;<br />
process implementation taProcess.impl<br />
subcomponents<br />
taTh: thread taThread.impl;<br />
connections<br />
C91: event data port taTh.pressEvent -> pressEvent;<br />
end taProcess.impl;<br />
The thread taTh is dispatched periodically, with a period <strong>of</strong> one second.<br />
When the thread is dispatched, the s<strong>in</strong>gle transition is applied once (s<strong>in</strong>ce the<br />
result<strong>in</strong>g state s0 is a complete state), <strong>and</strong> the action performed is to output<br />
the value 1 through the output port pressEvent:<br />
thread taThread<br />
features<br />
pressEvent: out event data port Behavior::<strong>in</strong>teger;<br />
properties<br />
Dispatch_Protocol => periodic;<br />
Period => 1 sec;<br />
end taThread;<br />
thread implementation taThread.impl<br />
annex behavior_specification {**<br />
states<br />
s0: <strong>in</strong>itial complete state;<br />
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transitions<br />
s0 -[ ]-> s0 { pressEvent!(1); };<br />
**};<br />
end taThread.impl;<br />
The other components are def<strong>in</strong>ed <strong>in</strong> a similar way. The follow<strong>in</strong>g presents<br />
the implementation <strong>of</strong> the X-ray mach<strong>in</strong>e thread, which shows a transition system<br />
with state variables, <strong>and</strong> where each transition guard conta<strong>in</strong>s a test on<br />
the existence <strong>of</strong> events/data <strong>in</strong> the <strong>in</strong>put ports, <strong>and</strong> on the value <strong>of</strong> the data<br />
received (<strong>in</strong>Message). S<strong>in</strong>ce the Dispatch_Protocol is aperiodic, this thread<br />
is activated upon receiv<strong>in</strong>g <strong>in</strong>put:<br />
thread xmThread<br />
features<br />
contrInput: <strong>in</strong> event data port Behavior::<strong>in</strong>teger;<br />
timeoutInput: <strong>in</strong> event port;<br />
timeoutReq: out event data port Behavior::<strong>in</strong>teger;<br />
properties<br />
Dispatch_Protocol => aperiodic;<br />
end xmThread;<br />
thread implementation xmThread.impl<br />
annex behavior_specification {**<br />
states<br />
idle: <strong>in</strong>itial complete state;<br />
xray, pend<strong>in</strong>gXray: complete state;<br />
state variables<br />
xrayDone: Behavior::boolean;<br />
pend<strong>in</strong>gTimeout: Behavior::<strong>in</strong>teger;<br />
xrayDuration: Behavior::<strong>in</strong>teger;<br />
<strong>in</strong>Message: Behavior::<strong>in</strong>teger;<br />
<strong>in</strong>itial<br />
xrayDone := false;<br />
pend<strong>in</strong>gTimeout := 2;<br />
xrayDuration := 1;<br />
transitions<br />
idle -[contrInput?(<strong>in</strong>Message) when <strong>in</strong>Message = 1]-> pend<strong>in</strong>gXray<br />
{timeoutReq!(pend<strong>in</strong>gTimeout);};<br />
pend<strong>in</strong>gXray -[timeoutInput?]-> xray {timeoutReq!(xrayDuration);};<br />
xray -[timeoutInput?]-> idle {xrayDone:=true;};<br />
**};<br />
end xmThread.impl;<br />
3.2 Real-Time Maude <strong>Semantics</strong> <strong>of</strong> <strong>AADL</strong><br />
<strong>AADL</strong> is a model<strong>in</strong>g notation whose st<strong>and</strong>ard is described <strong>in</strong>formally <strong>in</strong> English<br />
without a precise semantics. Unavoidably this means that there are various<br />
ambiguities <strong>in</strong> the st<strong>and</strong>ard, <strong>in</strong>clud<strong>in</strong>g its behavioral annex. However, formal
specification <strong>and</strong> analysis are mean<strong>in</strong>gless without a precise semantics. This section<br />
outl<strong>in</strong>es the rewrit<strong>in</strong>g logic semantics for the behavioral subset <strong>of</strong> <strong>AADL</strong><br />
presented <strong>in</strong> Section 3.1. We show first how an <strong>AADL</strong> model can be represented<br />
<strong>in</strong> Real-Time Maude, <strong>and</strong> then def<strong>in</strong>e the dynamics <strong>of</strong> <strong>AADL</strong> for models that<br />
use the behavioral annex.<br />
Represent<strong>in</strong>g <strong>AADL</strong> <strong>Models</strong> <strong>in</strong> Real-Time Maude<br />
Components. The semantics <strong>of</strong> a component-based language such as <strong>AADL</strong> can<br />
naturally be def<strong>in</strong>ed <strong>in</strong> an object-oriented style, where each <strong>in</strong>stance <strong>of</strong> a component<br />
is modeled as an object. The hierarchical structure <strong>of</strong> <strong>AADL</strong> components<br />
is reflected <strong>in</strong> the nested (“Russian dolls”) structure <strong>of</strong> objects, <strong>in</strong> which an attribute<br />
<strong>of</strong> an object/component conta<strong>in</strong>s the subcomponents <strong>of</strong> the object as a<br />
multiset <strong>of</strong> objects.<br />
Any <strong>AADL</strong> component <strong>in</strong>stance is represented as an object <strong>in</strong>stance <strong>of</strong> a<br />
subclass <strong>of</strong> the follow<strong>in</strong>g class Component, which conta<strong>in</strong>s the attributes common<br />
to all k<strong>in</strong>ds <strong>of</strong> components (systems, processes, threads, etc.):<br />
class Component | features : Configuration,<br />
subcomponents : Configuration,<br />
connections : ConnectionSet,<br />
properties : Properties,<br />
modes : ModeTransitionSystem,<br />
<strong>in</strong>Modes : ModeNameSet .<br />
The attribute features denotes the features <strong>of</strong> a component (i.e., its ports), represented<br />
as a multiset <strong>of</strong> Port objects (see below). The subcomponents attribute<br />
denotes the multiset <strong>of</strong> subcomponents <strong>of</strong> the object. The connections attribute<br />
denotes the set <strong>of</strong> port connections <strong>of</strong> the objects (see below). The properties<br />
attribute denotes the properties <strong>of</strong> the component, which <strong>in</strong> our case are the<br />
dispatch protocol <strong>and</strong> the value constra<strong>in</strong>ts for thread components. The modes<br />
attribute conta<strong>in</strong>s the object’s mode transition system. F<strong>in</strong>ally, the <strong>in</strong>Modes<br />
attribute gives the set <strong>of</strong> modes (<strong>of</strong> the immediate conta<strong>in</strong><strong>in</strong>g component) <strong>in</strong><br />
which the component is available (if the component is not a mode-specific subcomponent<br />
<strong>of</strong> the conta<strong>in</strong><strong>in</strong>g component, then this attribute has the special value<br />
allModes).<br />
For our chosen subset <strong>of</strong> <strong>AADL</strong>, the classes System <strong>and</strong> Process, denot<strong>in</strong>g<br />
system <strong>and</strong> process components, do not have any other attributes than those<br />
they <strong>in</strong>herit from Component:<br />
class System . subclass System < Component .<br />
class Process . subclass Process < Component .<br />
The Thread class is the follow<strong>in</strong>g subclass <strong>of</strong> Component:<br />
class Thread | behavior : ThreadBehavior,<br />
status : ThreadStatus,<br />
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subclass Thread < Component .<br />
threadType : ThreadName,<br />
implementationType : ImplName,<br />
deactivated : Bool .<br />
The behavior attribute denotes the locations <strong>and</strong> the state variables <strong>and</strong> their<br />
values <strong>of</strong> the transition system associated with the thread. To avoid carry<strong>in</strong>g<br />
around the (sometimes quite large) set <strong>of</strong> transitions associated with the<br />
thread, the transitions themselves are def<strong>in</strong>ed as the value <strong>of</strong> the expression<br />
transitions(threadT ype,implName). To access its transitions, a thread object<br />
must therefore conta<strong>in</strong> its threadName <strong>and</strong> implName. The status <strong>in</strong>dicates<br />
the current status <strong>of</strong> the thread (active, completed, suspended, etc.). The attribute<br />
deactivated <strong>in</strong>dicates whether the thread is deactivated as a result <strong>of</strong><br />
a mode transition somewhere <strong>in</strong> the component hierarchy.<br />
Ports. Any port is an object <strong>in</strong>stance <strong>of</strong> a subclass <strong>of</strong> the follow<strong>in</strong>g class Port,<br />
whose only attribute denotes the list <strong>of</strong> messages (events or data) currently <strong>in</strong><br />
the port’s buffer:<br />
class Port | buffer : MsgList .<br />
Several subclasses <strong>of</strong> Port def<strong>in</strong>e outgo<strong>in</strong>g <strong>and</strong> <strong>in</strong>com<strong>in</strong>g ports, as well as<br />
event ports <strong>and</strong> event data ports. The subclass InThreadPort also conta<strong>in</strong>s an<br />
<strong>in</strong>ternalBuffer <strong>and</strong> a fresh flag (which <strong>in</strong>dicates whether there are new messages<br />
<strong>in</strong> the thread’s <strong>in</strong>ternal buffer that have not yet been treated). In addition,<br />
the dequeueProtocol is def<strong>in</strong>ed <strong>in</strong> the InEventThreadPort. It determ<strong>in</strong>es how<br />
many items are dequeued from the buffer when a thread dispatches:<br />
class InPort . class OutPort .<br />
subclass InPort OutPort < Port .<br />
...<br />
class InThreadPort | <strong>in</strong>ternalBuffer : MsgList, fresh : Bool .<br />
subclass InThreadPort < InPort .<br />
class InEventThreadPort | dequeueProtocol : DequeuePolicy .<br />
subclass InEventThreadPort < InThreadPort InEventPort .<br />
sort DequeuePolicy .<br />
ops allItems oneItem : -> DequeuePolicy [ctor] .<br />
Connections. The follow<strong>in</strong>g sorts def<strong>in</strong>e, respectively, port names, s<strong>in</strong>gle port<br />
connections, <strong>and</strong> sets <strong>of</strong> such connections:<br />
sort PortName . subsort PortId < PortName .<br />
op _._ : ComponentId PortId -> PortName [ctor] .<br />
sort Connection .
op _-->_ : PortName PortName -> Connection [ctor] .<br />
sort ConnectionSet . subsort Connection < ConnectionSet .<br />
op none : -> Connection [ctor] .<br />
op _;_ : ConnectionSet ConnectionSet -> ConnectionSet [ctor assoc comm id: none] .<br />
An (immediate) level-up connection is therefore modeled as a term C.P --> P ′ ,<br />
where C is the identifier <strong>of</strong> the subcomponent <strong>in</strong> which the source port with<br />
identifier P resides. The dest<strong>in</strong>ation port is the port with name P ′ <strong>in</strong> the “current”<br />
component. Likewise, immediate same-level <strong>and</strong> level-down connections<br />
are terms <strong>of</strong> the forms, respectively, P1 --> P2 <strong>and</strong> P --> C.P ′ . We have not yet<br />
def<strong>in</strong>ed the semantics <strong>of</strong> delayed connections.<br />
Connections can be mode-specific; such connections are def<strong>in</strong>ed as terms <strong>of</strong><br />
the form P --> P ′ <strong>in</strong> modes (mk . . . ml):<br />
op _-->_<strong>in</strong>‘modes_ : PortName PortName ModeNameSet -> Connection [ctor] .<br />
Represent<strong>in</strong>g Thread Behavior. As mentioned above, to save space <strong>in</strong> the term<br />
representation <strong>of</strong> an <strong>AADL</strong> component by not carry<strong>in</strong>g around the transition<br />
rules, which do not change, <strong>of</strong> a thread <strong>in</strong> its state, we divide the representation<br />
<strong>of</strong> the transition system associated with a thread <strong>in</strong>to two parts:<br />
1. The locations <strong>and</strong> the current values <strong>of</strong> the local variables <strong>of</strong> the transition<br />
system are represented <strong>in</strong> the behavior attribute <strong>of</strong> the correspond<strong>in</strong>g thread<br />
objects as a term<br />
states<br />
current: s complete: s1 . . . sk others: sk+1 . . . sn<br />
state variables<br />
var1 |-> val1 . . . varm |-> valuem<br />
2. The transitions <strong>of</strong> any thread <strong>of</strong> “thread type” threadT ype <strong>and</strong> implementation<br />
impl are represented by a term<br />
transitions<br />
s -[guard]-> s ′ {actions} ;<br />
. . .<br />
s ′′ -[guard ′ ]-> s ′ {actions ′ }<br />
that is declared to be equal to the term transitions(threadT ype,impl).<br />
The constructor for the first part <strong>of</strong> transition systems is declared<br />
sort ThreadBehavior .<br />
op states_state‘variables_ : LocationDeclSet Valuation -> ThreadBehavior [ctor] .<br />
sorts Location LocationSet .<br />
subsort Location < LocationSet .<br />
op emptyLocationSet : -> LocationSet [ctor] .<br />
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op __ : LocationSet LocationSet -> LocationSet<br />
[ctor assoc comm id: emptyLocationSet] .<br />
sorts LocationDecl LocationDeclSet .<br />
subsort LocationDecl < LocationDeclSet .<br />
op current:_ : Location -> LocationDecl [ctor] .<br />
op <strong>in</strong>itial:_ : Location -> LocationDecl .<br />
ops complete:_ other:_ : LocationSet -> LocationDecl [ctor] .<br />
op noLocDecl : -> LocationDeclSet [ctor] .<br />
op __ : LocationDeclSet LocationDeclSet -> LocationDeclSet<br />
[ctor assoc comm id: noLocDecl] .<br />
We have also def<strong>in</strong>ed some additional “syntactic sugar” functions (e.g., allow<strong>in</strong>g<br />
the def<strong>in</strong>ition <strong>of</strong> <strong>in</strong>itial states, for skipp<strong>in</strong>g the declaration <strong>of</strong> the store when<br />
no state variables are declared, etc.) that reduce to terms <strong>of</strong> the above form.<br />
The set <strong>of</strong> transitions, locations, <strong>and</strong> variable mapp<strong>in</strong>gs have the structure <strong>of</strong> a<br />
multiset, us<strong>in</strong>g a b<strong>in</strong>ary multiset union operator that is declared to be associative<br />
<strong>and</strong> commutative.<br />
For example, the set <strong>of</strong> transitions is def<strong>in</strong>ed as follows:<br />
sort Transition .<br />
op _-‘[_‘]->_‘{_‘} : Location TransGuard Location StatementList<br />
-> Transition [ctor] .<br />
sort TransitionSet .<br />
subsort Transition < TransitionSet .<br />
op emptyTransitionSet : -> TransitionSet [ctor] .<br />
op _;_ : TransitionSet TransitionSet -> TransitionSet<br />
[ctor assoc comm id: emptyTransitionSet] .<br />
As already mentioned, the transition table is given by the function transitions<br />
hav<strong>in</strong>g the memo attribute, which means that the transitions for each thread implemented<br />
are memorized:<br />
op transitions : ThreadName ImplName -> TransitionSet [memo] .<br />
Translat<strong>in</strong>g an <strong>AADL</strong> Model <strong>in</strong>to a Real-Time Maude Module. We now show how<br />
an <strong>AADL</strong> model can be represented as a Real-Time Maude module. One <strong>of</strong> the<br />
ma<strong>in</strong> goals <strong>of</strong> our semantics is to make the “representational distance” between<br />
the <strong>AADL</strong> specification <strong>and</strong> the correspond<strong>in</strong>g Real-Time Maude module as<br />
small as possible, so that we can automatically translate an <strong>AADL</strong> model to a<br />
very similar-look<strong>in</strong>g Real-Time Maude module.<br />
Consider a type declaration <strong>of</strong> a component (System, Process, or Thread):<br />
system typeNname<br />
[features: ports]<br />
[properties: properties]<br />
end typeName;
This declaration b<strong>in</strong>ds the name to a set <strong>of</strong> ports <strong>and</strong> properties. We can therefore<br />
consider system as a function that, given a name, returns the <strong>in</strong>terface <strong>of</strong><br />
that name:<br />
op system : SystemName ~> FeaturesAndProperties .<br />
A component implementation, such as<br />
system implementation typeName.implName<br />
...<br />
end typeName.implName;<br />
def<strong>in</strong>es an object/component template, which is <strong>in</strong>stantiated to a concrete <strong>in</strong>stance<br />
<strong>of</strong> the component <strong>in</strong> <strong>AADL</strong> declarations <strong>of</strong> the form<br />
<strong>in</strong>stanceName: system typeName.implName<br />
<strong>and</strong><br />
<strong>in</strong>stanceName: system typeName.implName <strong>in</strong> modes (mode names)<br />
Therefore, <strong>in</strong> our Real-Time Maude semantics, the above component implementation<br />
declaration translates to an equation<br />
var INSTANCE-NAME : Oid . var MNS : ModeNameSet .<br />
eq INSTANCE-NAME system typeName . implName <strong>in</strong> modes MNS =<br />
< INSTANCE-NAME : System | features : features(system(typeName)),<br />
properties : properties(system(typeName)),<br />
<strong>in</strong>Modes : MNS,<br />
subcomponents : ...,<br />
connections : ...,<br />
... ><br />
In addition, the equation<br />
eq SI:SystemId system SN:SystemName . IN:ImplName =<br />
SI:SystemId system SN:SystemName . IN:ImplName <strong>in</strong> modes allModes .<br />
allows us to declare component <strong>in</strong>stances that are not mode-dependent.<br />
A concrete component <strong>in</strong>stance, declared <strong>in</strong> <strong>AADL</strong> as<br />
<strong>in</strong>stanceName: system typeName.implName<br />
is therefore translated directly <strong>in</strong>to the Real-Time Maude term<br />
<strong>in</strong>stanceName system typeName . implName<br />
which equals the desired object<br />
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18<br />
< <strong>in</strong>stanceName : System | features : features(system(typeName)),<br />
properties : properties(system(typeName)),<br />
<strong>in</strong>Modes : allModes,<br />
subcomponents : ...,<br />
connections : ...,<br />
... ><br />
Likewise, for mode-specific system components, the term<br />
<strong>in</strong>stanceName system typeName . implName <strong>in</strong> modes (mode names)<br />
equals the object<br />
< <strong>in</strong>stanceName : System | features : features(system(typeName)),<br />
properties : properties(system(typeName)),<br />
<strong>in</strong>Modes : mode names,<br />
subcomponents : ...,<br />
connections : ...,<br />
... ><br />
This scheme applies <strong>in</strong> exactly the same way to the other k<strong>in</strong>ds <strong>of</strong> components<br />
(Process <strong>and</strong> Thread), so that the <strong>AADL</strong> model <strong>and</strong> its Real-Time Maude<br />
representation are textually fairly similar, as shown <strong>in</strong> the follow<strong>in</strong>g example.<br />
Example 1. Consider the <strong>AADL</strong> model <strong>of</strong> the X-ray/ventilator mach<strong>in</strong>e system<br />
<strong>in</strong> Section 3.1. The declaration <strong>of</strong> the type <strong>of</strong> the entire system<br />
system Wholesys<br />
end Wholesys;<br />
is translated <strong>in</strong>to the Real-Time Maude equation<br />
eq system(Wholesys) = features none properties noProperty .<br />
The <strong>AADL</strong> implementation def<strong>in</strong>ition<br />
system implementation Wholesys.imp<br />
subcomponents<br />
Test_Activator: system TA.impl;<br />
XRayMach<strong>in</strong>e: system XM.impl;<br />
VentilatorMach<strong>in</strong>e: system VM.impl;<br />
Controller: system Controller.impl;<br />
connections<br />
C01: event data port Controller.xmContrOutput -><br />
XrayMach<strong>in</strong>e.controllerInput;<br />
C02: event data port Controller.vmContrOutput -><br />
VentilatorMach<strong>in</strong>e.controllerInput;<br />
C03: event data port VentilatorMach<strong>in</strong>e.feedback -> Controller.feedback;<br />
C04: event data port TestActivator.pressEvent -><br />
Controller.comm<strong>and</strong>Input;<br />
end Wholesys.imp;
is translated <strong>in</strong>to the Real-Time Maude equation<br />
eq INSTANCE-NAME system Wholesys . imp <strong>in</strong> modes MNS =<br />
< INSTANCE-NAME : System | modes : noModes, <strong>in</strong>Modes : MNS,<br />
features : features(system(Wholesys)),<br />
subcomponents : (TestActivator system TA . impl)<br />
(XRayMach<strong>in</strong>e system XM . impl)<br />
(VentilatorMach<strong>in</strong>e system VM . impl)<br />
(Controller system Controller . impl),<br />
connections :<br />
(Controller . xmContrOutput --> XRayMach<strong>in</strong>e . controllerInput) ;<br />
(Controller . vmContrOutput --> VentilatorMach<strong>in</strong>e . controllerInput) ;<br />
(VentilatorMach<strong>in</strong>e . feedback --> Controller . feedback) ;<br />
(TestActivator . pressEvent --> Controller . comm<strong>and</strong>Input),<br />
properties : properties(system(Wholesys)) > .<br />
Likewise, the <strong>AADL</strong> model <strong>of</strong> the test activator process<br />
system TA<br />
features<br />
press_event: out event data port Behavior::<strong>in</strong>teger;<br />
end TA;<br />
system implementation TA.impl<br />
subcomponents<br />
taPr: process taProcess.impl;<br />
connections<br />
C90: event data port taPr.pressEvent -> pressEvent;<br />
end TA.impl;<br />
is translated l<strong>in</strong>e by l<strong>in</strong>e <strong>in</strong>to the Real-Time Maude equations<br />
eq system(TA) = features (pressEvent out event data port) .<br />
eq INSTANCE-NAME system TA . impl <strong>in</strong> modes MNS =<br />
< INSTANCE-NAME : System | modes : noModes, <strong>in</strong>Modes : MNS,<br />
features : features(system(TA)),<br />
subcomponents : (taPr process taProcess . impl),<br />
connections : (taPr . pressEvent --> pressEvent),<br />
properties : properties(system(TA)) > .<br />
where pressEvent out event data port equals a port object accord<strong>in</strong><strong>in</strong>g the<br />
follow<strong>in</strong>g def<strong>in</strong>ition:<br />
op _out‘event‘data‘port : PortId -> Object .<br />
eq P:PortId out event data port = < P:PortId : OutEventDataPort | buffer : nil > .<br />
In the same style, we can def<strong>in</strong>e the translation <strong>of</strong> the test activator thread<br />
implementation. In <strong>AADL</strong>, this thread is def<strong>in</strong>ed as follows:<br />
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20<br />
thread taThread<br />
features<br />
press_event: out event data port Behavior::<strong>in</strong>teger;<br />
properties<br />
Dispatch_Protocol => periodic;<br />
Period => 1 sec;<br />
end taThread;<br />
thread implementation taThread.impl<br />
annex behavior_specification {**<br />
states<br />
s0: <strong>in</strong>itial complete state;<br />
transitions<br />
s0 -[ ]-> s0 { pressEvent!(1); };<br />
**};<br />
end taThread.impl;<br />
The correspond<strong>in</strong>g Real-Time Maude equations are aga<strong>in</strong> very similar:<br />
eq thread(taThread) = features (pressEvent out event data thread port)<br />
properties periodic-dispatch(1) .<br />
eq INSTANCE-NAMEthread taThread . impl <strong>in</strong> modes MNS =<br />
< INSTANCE-NAME : Thread | modes : noModes, <strong>in</strong>Modes : MNS,<br />
features : features(thread(taThread)),<br />
threadType : taThread,<br />
implementationType : impl,<br />
subcomponents : none,<br />
connections : none,<br />
properties : properties(thread(taThread)),<br />
behavior : state variables noVariables<br />
states <strong>in</strong>itial: s0 complete: s0 > .<br />
eq transitions(taThread, impl) =<br />
(s0 -[]-> s0 {(pressEvent ! (1))}) .<br />
It is worth notic<strong>in</strong>g that the deactivated attribute was not def<strong>in</strong>ed <strong>in</strong> the<br />
above equations, s<strong>in</strong>ce it is impossible to see from only the def<strong>in</strong>ition <strong>of</strong> the thread<br />
type <strong>and</strong> implementation whether or not a thread is <strong>in</strong>itially deactivated. This<br />
is due to the fact that deactivation may follow from mode-specific components<br />
much higher <strong>in</strong> the conta<strong>in</strong>ment hierarchy. A function <strong>in</strong>itializeThreads is<br />
therefore applied to fully def<strong>in</strong>e the <strong>in</strong>itial state by def<strong>in</strong><strong>in</strong>g the <strong>in</strong>itial deactivated<br />
value for each thread object.<br />
Dynamics. This section formalizes the operational semantics <strong>of</strong> <strong>AADL</strong> <strong>in</strong> Real-<br />
Time Maude. Unavoidably, s<strong>in</strong>ce <strong>AADL</strong> does not have a precise semantics, our<br />
semantic def<strong>in</strong>itions are a formal semantics for <strong>AADL</strong> <strong>and</strong> <strong>in</strong>volve an <strong>in</strong>terpretation<br />
<strong>of</strong> what the <strong>in</strong>formal <strong>and</strong> sometimes ambiguous descriptions <strong>in</strong> the st<strong>and</strong>ard<br />
mean. The dynamics is def<strong>in</strong>ed by equations <strong>and</strong> rewrite rules specify<strong>in</strong>g:
– “message” transportation,<br />
– mode switches,<br />
– thread dispatch,<br />
– thread execution,<br />
– nondeterm<strong>in</strong>istically assign<strong>in</strong>g values to a set <strong>of</strong> variables, given a value<br />
constra<strong>in</strong>t, <strong>and</strong><br />
– timed behavior.<br />
Message Pass<strong>in</strong>g. In the spirit <strong>of</strong> the “traditional” Maude model for message<br />
transmission — where message transmission from source to dest<strong>in</strong>ation is abstractly<br />
modeled by the state hav<strong>in</strong>g a multiset structure — we use equations to<br />
model the transmission <strong>of</strong> messages from source port to dest<strong>in</strong>ation port along<br />
a series <strong>of</strong> connections.<br />
To transmit a list ML <strong>of</strong> messages (that is, events <strong>and</strong>/or data), an out port<br />
puts transfer(ML) <strong>in</strong>to its buffer. The follow<strong>in</strong>g equation models the transmission<br />
<strong>of</strong> a message list along a level-up connection C1 . P1 --> P from the out<br />
port P1 <strong>of</strong> the subcomponent C1 to the out port P <strong>of</strong> the supercomponent C. As<br />
a result <strong>of</strong> apply<strong>in</strong>g the equation, the port P now has the value transfer(ML),<br />
<strong>and</strong> the subcomponent’s port buffer is empty:<br />
op transfer : MsgList -> MsgList [ctor] .<br />
vars C C1 C2 : ComponentId . vars P P1 P2 : PortId .<br />
vars PORTS PORTS2 OTHER-COMPONENTS : Configuration .<br />
vars ML ML’ : MsgList . var CONXS : ConnectionSet .<br />
eq < C : Component |<br />
features : < P : OutPort | buffer : nil > PORTS,<br />
subcomponents :<br />
< C1 : Component |<br />
features : < P1 : OutPort | buffer : transfer(ML) > PORTS2 ><br />
OTHER-COMPONENTS,<br />
connections : (C1 . P1 --> P) ; CONXS ><br />
=<br />
< C : Component |<br />
features : < P : OutPort | buffer : transfer(ML) > PORTS,<br />
subcomponents :<br />
< C1 : Component | features : < P1 : OutPort | buffer : nil > PORTS2 ><br />
OTHER-COMPONENTS > .<br />
The follow<strong>in</strong>g equation models the transmission <strong>of</strong> a message list follow<strong>in</strong>g a<br />
same-level connection between the two subcomponents C1 <strong>and</strong> C2:<br />
eq < C : Component |<br />
subcomponents :<br />
< C1 : Component |<br />
features : < P1 : OutPort | buffer : transfer(ML) > PORTS ><br />
< C2 : Component |<br />
features : < P2 : InPort | buffer : nil > PORTS2 ><br />
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OTHER-COMPONENTS,<br />
connections : (C1 . P1 --> C2 . P2) ; CONXS ><br />
=<br />
< C : Component |<br />
subcomponents :<br />
< C1 : Component |<br />
features : < P1 : OutPort | buffer : nil > PORTS ><br />
< C2 : Component |<br />
features : < P2 : InPort | buffer : transfer(ML) > PORTS2 ><br />
OTHER-COMPONENTS > .<br />
This is a somewhat simplified version <strong>of</strong> the equations we actually use, s<strong>in</strong>ce we<br />
also allow 1-to-n same-level connections as well as mode-specific connections.<br />
F<strong>in</strong>ally, the follow<strong>in</strong>g equation models the transmission <strong>of</strong> a list <strong>of</strong> messages<br />
along a level-down connection. It is similar to a level-up connection, the only<br />
difference be<strong>in</strong>g that the dest<strong>in</strong>ation may already have some buffer contents;<br />
therefore, the list to be transferred is just appended to the buffer <strong>of</strong> the dest<strong>in</strong>ation<br />
port:<br />
eq < C : Component |<br />
features :<br />
< P : InPort | buffer : transfer(ML) > PORTS,<br />
subcomponents :<br />
< C1 : Component | features : < P1 : InPort | buffer : ML’ > PORTS2 ><br />
OTHER-COMPONENTS,<br />
connections : (P --> C1 . P1) ; CONXS ><br />
=<br />
< C : Component |<br />
features : < P : InPort | buffer : nil > PORTS,<br />
subcomponents :<br />
< C1 : Component | features : < P1 : InPort | buffer : ML’ :: transfer(ML) ><br />
PORTS2 ><br />
OTHER-COMPONENTS > .<br />
Thread Status <strong>and</strong> Mode Switches. The execution status <strong>of</strong> a thread can be any<br />
<strong>of</strong> the follow<strong>in</strong>g:<br />
Active: The thread is ready to execute a state transition.<br />
Completed: The thread has completed its execution <strong>in</strong> this dispatch <strong>and</strong> waits<br />
for its next dispatch.<br />
Sleep<strong>in</strong>g: The thread is suspended, <strong>and</strong> will resume execution after a given<br />
amount <strong>of</strong> time.<br />
Inactive: The thread is not part <strong>of</strong> the “active” mode <strong>of</strong> the system.<br />
A mode switch has the effect <strong>of</strong> deactivat<strong>in</strong>g <strong>and</strong> activat<strong>in</strong>g threads to respond<br />
to dispatches. A thread becomes <strong>in</strong>active as the result <strong>of</strong> a mode change<br />
if it is not part <strong>of</strong> the new mode. An <strong>in</strong>active thread cannot be dispatched for<br />
execution. An <strong>in</strong>active thread can be activated as the result <strong>of</strong> a mode change,<br />
<strong>in</strong> which case the thread enters the completed status, from where it can respond
to future dispatches. When a thread <strong>in</strong> the completed status receives a dispatch<br />
request, the thread enters the active status to perform the computation. Upon<br />
successful completion <strong>of</strong> the computation, the thread returns to the completed<br />
status. Once an active thread executes a delay action, it enters the sleep<strong>in</strong>g status,<br />
suspends for a period <strong>of</strong> time, <strong>and</strong> becomes active after that time period.<br />
Mode switch is modeled by the follow<strong>in</strong>g rewrite rule:<br />
rl [modeSwitch] :<br />
< C : Component |<br />
features :<br />
(< P : InEventPort | buffer : transfer(ML) :: ML’ > PORTS),<br />
modes : current: MN1<br />
transitions: (MN1 -[P , PIS]-> MN2 ) ; MTSET,<br />
subcomponents : SUBCOMPONENTS ><br />
=><br />
< C : Component |<br />
features : (< P : InEventPort | buffer : nil > PORTS),<br />
modes : current: MN2 transitions: (MN1 -[P , PIS]-> MN2) ; MTSET,<br />
subcomponents : modeSwitch(SUBCOMPONENTS, MN1, MN2) > .<br />
where the modeSwitch operation propagates the mode switch request to the<br />
subcomponents (by sett<strong>in</strong>g deactivated to true for the other threads to be<br />
suspended; <strong>and</strong> vice versa for the threads that should be activated).<br />
Thread Dispatch <strong>and</strong> Execution. Under a periodic dispatch protocol, a thread<br />
<strong>in</strong> completed status is dispatched when the “dispatch timer,” i.e., the second<br />
parameter T’ <strong>in</strong> the term periodic-dispatch(T,T’), is 0. As a result, the<br />
thread is dispatched, that is, its status is set to active, the “timer” is reset to<br />
the length T <strong>of</strong> a period, <strong>and</strong> the <strong>in</strong>put ports are “dispatched” as well:<br />
crl [periodic-dispatch] :<br />
< O : Thread | properties : periodic-dispatch(T, 0 ) ; TP,<br />
status : completed,<br />
features : PORTS ><br />
=><br />
< O : Thread | properties : periodic-dispatch(T, T) ; TP,<br />
status : active ,<br />
features : dispatchInputPorts(PORTS) ><br />
if not environmentThread(TP) .<br />
Likewise, when the dispatch protocol is aperiodic, <strong>and</strong> new events have arrived<br />
<strong>in</strong> some <strong>of</strong> the thread’s <strong>in</strong>put ports (that is, some <strong>of</strong> the messages <strong>in</strong> the<br />
port buffer have the wrapper transfer), <strong>and</strong> the thread is <strong>in</strong> completed status,<br />
then the thread is activated: 6<br />
6 In our <strong>AADL</strong> subset, we assume that any arriv<strong>in</strong>g event may dispatch an aperiodic<br />
thread.<br />
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24<br />
rl [aperiodic-<strong>in</strong>com<strong>in</strong>g-message] :<br />
< O : Thread | properties : aperiodic-dispatch PROPS,<br />
features :<br />
(< P : InEventThreadPort | buffer : ML :: transfer(ML’) ><br />
PORTS),<br />
status : completed ><br />
=><br />
< O : Thread | features :<br />
dispatchInputPorts(<br />
< P : InEventThreadPort | buffer : ML :: ML’ > PORTS),<br />
status : active > .<br />
The next rule specifies the execution <strong>of</strong> an active thread. If the thread is<br />
<strong>in</strong> state L1, <strong>and</strong> there is some transition from L1 whose guard evaluates to<br />
true, then the transition is executed. The result<strong>in</strong>g status is sleep<strong>in</strong>g(...)<br />
if some <strong>of</strong> the actions <strong>in</strong> the statement list SL are delay statements, the thread<br />
is completed or suspended if the result<strong>in</strong>g state L2 is a complete state, <strong>and</strong><br />
rema<strong>in</strong>s active otherwise:<br />
crl [execute-transition] :<br />
< O : Thread | status : active ,<br />
deactivated : false,<br />
features : PORTS,<br />
behavior : states (current: L1 ) LDS state variables VAL,<br />
threadType : TN, implementationType : IMPL ><br />
=><br />
< O : Thread | status : NEW-STATUS,<br />
features : (if NEW-STATUS == completed<br />
then transferData(NEW-PORTS)<br />
else NEW-PORTS fi),<br />
behavior : states (current: L2 ) LDS<br />
state variables NEW-VALUATION ><br />
if not environmentThread(TP)<br />
/\ ((L1 -[ GUARD ]-> L2 {SL}) ; TRANSITIONS) := transitions(TN, IMPL)<br />
/\ evalGuard(GUARD, dispatchInputPorts(PORTS), VAL)<br />
/\ transResult(NEW-PORTS, NEW-VALUATION, SLEEP-TIME) :=<br />
executeTransition(L1 -[ GUARD ]-> L2 SL, dispatchInputPorts(PORTS), VAL)<br />
/\ SLEEP := SLEEP-TIME > 0<br />
/\ NEW-STATUS := if SLEEP then sleep<strong>in</strong>g(SLEEP-TIME)<br />
else (if completeState(L2,LDS) then<br />
completed else active fi) fi .<br />
The function executeTransition executes a given transition <strong>in</strong> a state with a<br />
given set PORTS <strong>of</strong> ports <strong>and</strong> assignment VAL <strong>of</strong> the state variables. Its def<strong>in</strong>ition<br />
is straight-forward. The function returns a triple transResult(p, σ, t), where p<br />
is the state <strong>of</strong> the ports after the execution, σ is the result<strong>in</strong>g values <strong>of</strong> the state<br />
variables, <strong>and</strong> t is the sum <strong>of</strong> the delays <strong>in</strong> the transition actions. The transitions<br />
are modeled as a multiset <strong>of</strong> s<strong>in</strong>gle transitions; therefore, any <strong>of</strong> the enabled<br />
transitions can be nondeterm<strong>in</strong>istically selected <strong>in</strong> the match<strong>in</strong>g condition
((L1 -[ GUARD ]-> L2 {SL}) ; TRANSITIONS) := transitions(TN, IMPL)<br />
<strong>in</strong> the above rule.<br />
The follow<strong>in</strong>g rule models the behavior <strong>of</strong> a sleep<strong>in</strong>g thread when the rema<strong>in</strong><strong>in</strong>g<br />
sleep<strong>in</strong>g time is 0. The thread becomes active, completed, or suspended<br />
depend<strong>in</strong>g on whether or not its current state is a complete state <strong>and</strong>, if so,<br />
whether it should deactivate itself as a result <strong>of</strong> an earlier mode switch:<br />
rl [f<strong>in</strong>ish-sleep] :<br />
< O : Thread | status : sleep<strong>in</strong>g(0) ,<br />
deactivated : B,<br />
behavior : states current: L LDS state variables VAL ><br />
=><br />
< O : Thread | status : (if not completeState(L, LDS) then active else<br />
(if B then <strong>in</strong>active else completed fi) fi) > .<br />
Value Constra<strong>in</strong>ts. Consider aga<strong>in</strong> an “environment” thread which is supposed<br />
to nondeterm<strong>in</strong>istically generate n boolean values b1, . . . , bn, satisfy<strong>in</strong>g a constra<strong>in</strong>t<br />
ϕ(b1, . . . , bn), for its n boolean state variables.<br />
A straight-forward solution is to <strong>in</strong>itialize each bi to some “un<strong>in</strong>itialized”<br />
value, <strong>and</strong> then have two rules which assign an un<strong>in</strong>itialized boolean variable<br />
the values true <strong>and</strong> false, respectively. However, s<strong>in</strong>ce the number <strong>of</strong> Boolean<br />
vectors is exponential on the number <strong>of</strong> Boolean variables, this can quickly become<br />
too <strong>in</strong>efficient, s<strong>in</strong>ce it will generate too many assignments which do not<br />
satisfy ϕ. We <strong>in</strong>stead take advantage <strong>of</strong> Maude SAT solv<strong>in</strong>g features to easily<br />
def<strong>in</strong>e a function<br />
op allAssignments : Valuation BoolExpression -> ValuationSet [memo] .<br />
to generate the set <strong>of</strong> all possible variable assignments satisfy<strong>in</strong>g ϕ, <strong>and</strong> then<br />
have a rule that can nondeterm<strong>in</strong>istically select any <strong>of</strong> these assignments.<br />
In our model, the sort Valuation def<strong>in</strong>es a variable map. Sets <strong>of</strong> such variable<br />
maps can then be def<strong>in</strong>ed us<strong>in</strong>g an associative <strong>and</strong> commutative set union<br />
operator _;;_:<br />
subsort Valuation < ValuationSet .<br />
op emptyVS : -> ValuationSet [ctor] .<br />
op _;;_ : ValuationSet ValuationSet -> ValuationSet<br />
[ctor assoc comm id: emptyVS] .<br />
eq VAL ;; VAL = VAL .<br />
Now, whenever an environment thread is dispatched, the environment should<br />
reset its (Boolean) variables nondeterm<strong>in</strong>istically so that the <strong>in</strong>put constra<strong>in</strong>t is<br />
satisfied. In the follow<strong>in</strong>g rule<br />
vars VAL NEW-ASSIGNMENT : Valuation .<br />
var VS : ValuationSet .<br />
crl [env-periodic-dispatch] :<br />
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26<br />
< O : Thread | properties : periodic-dispatch(T, 0 ) ; IsEnvironment(true) ;<br />
InputConstra<strong>in</strong>ts(ϕ) ; TP,<br />
status : completed ,<br />
features : PORTS,<br />
behavior : states LDS state variables VAL ><br />
=><br />
< O : Thread | properties : periodic-dispatch(T, T ) ;<br />
IsEnvironment(true) ; InputConstra<strong>in</strong>ts(ϕ) ; TP,<br />
status : active ,<br />
features : dispatchInputPorts(PORTS),<br />
behavior : states LDS<br />
state variables NEW-ASSIGNMENT ><br />
if NEW-ASSIGNMENT ;; VS := allAssignments(<strong>in</strong>itializeToFalse(VAL), ϕ) .<br />
the variable NEW-ASSIGNMENT can match any <strong>of</strong> the maps def<strong>in</strong>ed by allAssignments(...,ϕ).<br />
The po<strong>in</strong>t is that such an assignment should be done each time a thread is dispatched,<br />
that is, each time the thread goes from completed to active.<br />
We have implemented this technique, <strong>and</strong> it has given us improved performance<br />
<strong>in</strong> the avionics case study reported <strong>in</strong> Section 4. For further efficiency:<br />
– The set <strong>of</strong> all legal assigments is not stored <strong>in</strong> the states; <strong>in</strong>stead the function<br />
allAssignments is called each time a new variable assignment is selected.<br />
– The frequently called function allAssignments is declared to have the attribute<br />
memo, so that the results <strong>of</strong> its computations are memorized by Maude<br />
(see [4]). Therefore, after the first computation <strong>of</strong> allAssignments(V,ϕ)<br />
each subsequent “computation” <strong>of</strong> allAssignments(V,ϕ) takes time O(1).<br />
Time Behavior. Follow<strong>in</strong>g the specification techniques proposed <strong>in</strong> [14], we<br />
model time elapse <strong>in</strong> the system by a s<strong>in</strong>gle tick rule<br />
vars T T’ T’’ : Time . vars SYSTEM C C’ PORTS : Configuration .<br />
var S : SystemId . var THR : ThreadId .<br />
var P : PortId . var PROPS : Properties .<br />
var TS : ThreadStatus . vars ML ML’ ML’’ : MsgList .<br />
crl {SYSTEM} => {delta(SYSTEM, T)} <strong>in</strong> time T if T Configuration [frozen (1)] .<br />
op mte : Configuration -> TimeInf [frozen (1)] .<br />
<strong>and</strong> distribute over the elements <strong>in</strong> a (sub)configuration:
eq delta(none, T) = none .<br />
ceq delta(C C’, T) = delta(C, T) delta(C’, T) if C =/= none <strong>and</strong> C’ =/= none .<br />
eq mte(none) = INF .<br />
ceq mte(C C’) = m<strong>in</strong>(mte(C), mte(C’)) if C =/= none <strong>and</strong> C’ =/= none .<br />
The important time behaviors that must be taken <strong>in</strong>to account when def<strong>in</strong><strong>in</strong>g<br />
these functions are:<br />
– Periodic threads must dispatch at the given time.<br />
– Threads <strong>in</strong> sleep status must exit this status when their sleep time expires.<br />
– Time must not elapse when there are “untreated” messages <strong>in</strong> the system,<br />
s<strong>in</strong>ce an aperiodic thread is dispatched when it receives a message. This<br />
ensures that signals are treated <strong>in</strong>stantaneously.<br />
– Time cannot advance when a thread is <strong>in</strong> active state, as the thread should<br />
execute a transition when it is active.<br />
– Deactivated threads should not impact time behavior.<br />
Time elapse therefore only affects the timer t <strong>in</strong> the periodic-dispatch(T,t)<br />
property <strong>of</strong> a thread, <strong>and</strong> the timer t ′ <strong>in</strong> the sleep<strong>in</strong>g(t ′ ) status <strong>of</strong> a thread,<br />
both <strong>of</strong> which are reduced accord<strong>in</strong>g to the elapsed time. The function delta<br />
does not affect a System component, except by propagat<strong>in</strong>g to the subcomponents:<br />
eq delta(< S : System | features : PORTS, subcomponents : C >, T) =<br />
< S : System | features : PORTS, subcomponents : delta(C, T) > .<br />
delta is def<strong>in</strong>ed <strong>in</strong> the same way for Process objects. For Thread objects, the<br />
delta function must decrease the possible “timers” as described below, tak<strong>in</strong>g<br />
<strong>in</strong>to account the possibility that some <strong>of</strong> these “timers” are mode-specific<br />
properties:<br />
eq delta(< THR : Thread | deactivated : false, subcomponents : C,<br />
status : TS, modes : MTS, properties : TP >, T)<br />
=<br />
< THR : Thread | subcomponents : delta(C, T),<br />
status : delta(TS, T),<br />
properties : delta(TP, MTS, T) > .<br />
op delta : ThreadStatus Time -> ThreadStatus .<br />
eq delta(sleep<strong>in</strong>g(T), T’) = sleep<strong>in</strong>g(T monus T’) .<br />
eq delta(TS, T’) = TS [owise] .<br />
op delta : Properties ModeTransitionSystem Time -> Properties .<br />
eq delta((periodic-dispatch(T, T’) ; TP), MTS, T’’) =<br />
periodic-dispatch(T, T’ monus T’’ ) ; TP .<br />
eq delta(((periodic-dispatch(T, T’) <strong>in</strong> modes (MN MNS)) ; TP),<br />
current: MN transitions: MODETRANSES, T’’) =<br />
(periodic-dispatch(T, T’ monus T’’) <strong>in</strong> modes (MN MNS)) ; TP .<br />
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28<br />
eq delta((sporadic-dispatch(T, T’) ; TP), MTS, T’’) =<br />
sporadic-dispatch(T, T’ monus T’’) ; TP .<br />
eq delta(((sporadic-dispatch(T, T’) <strong>in</strong> modes (MN MNS)) ; TP),<br />
current: MN transitions: MODETRANSES, T’’) =<br />
(sporadic-dispatch(T, T’ monus T’’) <strong>in</strong> modes (MN MNS)) ; TP .<br />
eq delta(TP, MTS, T) = TP [owise] .<br />
As for the function mte, it does not affect System or Process objects, but<br />
must ensure that mte is 0 when an “untreated” message list, that is, one <strong>of</strong> the<br />
form transfer(ml), is present <strong>in</strong> some port buffer; <strong>in</strong> addition, it must ensure<br />
that time cannot advance beyond the time at which a sleep<strong>in</strong>g thread should<br />
wake up, or beyond the time at which a periodic thread should dispatch. In<br />
addition, time cannot advance when a thread is active:<br />
eq mte(< S : System | features : PORTS, subcomponents : C >) =<br />
m<strong>in</strong>(mte(PORTS), mte(C)) .<br />
eq mte(< THR : Thread | deactivated : B, features : PORTS, subcomponents : C,<br />
status : TS, properties : TP, modes : MTS >)<br />
=<br />
if B then INF else m<strong>in</strong>(mte(PORTS), mte(C), mte(TS), mte(TP, MTS)) fi .<br />
eq mte(< P : Port | buffer : ML :: transfer(ML’) :: ML’’ >) = 0 .<br />
eq mte(< P : Port | buffer : ML >) = INF [owise] .<br />
op mte : ThreadStatus -> TimeInf .<br />
eq mte(active) = 0 .<br />
eq mte(completed) = INF .<br />
eq mte(sleep<strong>in</strong>g(T)) = T .<br />
eq mte(<strong>in</strong>active) = INF .<br />
op mte : Properties ModeTransitionSystem -> TimeInf .<br />
eq mte(periodic-dispatch(T, T’) ; TP, MTS) = T’ .<br />
eq mte((periodic-dispatch(T, T’) <strong>in</strong> modes (MN MNS)) ; TP,<br />
current: MN transitions: MODETRANSES) = T’ .<br />
eq mte(TP, MTS) = INF [owise] .<br />
3.3 <strong>Formal</strong> <strong>Analysis</strong> <strong>of</strong> <strong>AADL</strong> <strong>Models</strong> <strong>in</strong> Real-Time Maude<br />
This section illustrates how the Real-Time Maude module correspond<strong>in</strong>g to an<br />
<strong>AADL</strong> model can be formally analyzed. In particular, we present some helpful<br />
functions allow<strong>in</strong>g the user to def<strong>in</strong>e desired properties without hav<strong>in</strong>g to<br />
underst<strong>and</strong> the details <strong>of</strong> the Real-Time Maude representation <strong>of</strong> an <strong>AADL</strong><br />
component.<br />
Def<strong>in</strong><strong>in</strong>g Initial States. An <strong>AADL</strong> system def<strong>in</strong>ition declares a template for<br />
the component. An <strong>in</strong>itial state is an <strong>in</strong>stance <strong>of</strong> such a template. For example,
<strong>in</strong> our medical example, assum<strong>in</strong>g that MAIN is a constant <strong>of</strong> sort SystemId <strong>of</strong><br />
System object names, a typical <strong>in</strong>itial state is<br />
<strong>in</strong>itializeThreads({MAIN system Wholesys . impl})<br />
A first form <strong>of</strong> formal analysis consists <strong>of</strong> simulat<strong>in</strong>g one <strong>of</strong> the many possible<br />
system behaviors up to a given duration us<strong>in</strong>g timed rewrit<strong>in</strong>g: 7<br />
Maude> (tfrew <strong>in</strong>itializeThreads({MAIN system Wholesys . impl}) <strong>in</strong> time < 20 .)<br />
Reachability <strong>Analysis</strong>. Real-Time Maude’s tsearch, respectively utsearch,<br />
comm<strong>and</strong> can be used to analyze whether or not a state match<strong>in</strong>g a given pattern<br />
<strong>and</strong> satisfy<strong>in</strong>g a given condition pattern can be reached from a given <strong>in</strong>itial state<br />
with<strong>in</strong> a given time <strong>in</strong>terval, respectively without any time limit.<br />
Def<strong>in</strong><strong>in</strong>g the appropriate state pattern <strong>in</strong> general requires underst<strong>and</strong><strong>in</strong>g the<br />
Real-Time Maude representation <strong>of</strong> the <strong>AADL</strong> component be<strong>in</strong>g analyzed. To<br />
avoid requir<strong>in</strong>g the user <strong>of</strong> our tool to know this Real-Time Maude representation,<br />
our tool def<strong>in</strong>es some useful functions. The term<br />
value <strong>of</strong> v <strong>in</strong> component fullComponentName <strong>in</strong> globalComponent<br />
returns the value <strong>of</strong> the state variable v <strong>in</strong> the thread identified by the full<br />
component name fullComponentName <strong>in</strong> the system <strong>in</strong> state globalComponent.<br />
The full component name is def<strong>in</strong>ed as a ->-separated path <strong>of</strong> component names,<br />
from the outermost to the <strong>in</strong>nermost. Likewise, the term<br />
location <strong>of</strong> component fullComponentName <strong>in</strong> globalComponent<br />
gives the current location/state <strong>in</strong> the transition system <strong>in</strong> the given thread. We<br />
have also def<strong>in</strong>ed useful functions for extract<strong>in</strong>g the contents <strong>of</strong> port buffers, as<br />
well as the content <strong>of</strong> a thread’s <strong>in</strong>ternal port buffer, by way <strong>of</strong> two functions<br />
getBuffer <strong>and</strong> getInternalBuffer.<br />
Example 2. In our medical devices example, the thread MAIN -> XRayMach<strong>in</strong>e<br />
-> xmPr -> xmTh denotes the full component name <strong>of</strong> the xmTh thread component,<br />
<strong>and</strong> the term<br />
location <strong>of</strong> component (MAIN -> XRayMach<strong>in</strong>e -> xmPr -> xmTh)<br />
<strong>in</strong> (MAIN system Wholesys . impl)<br />
equals the current location (or “state”) <strong>in</strong> the thread xmTh <strong>in</strong> the (<strong>in</strong>itial) state<br />
(MAIN system Wholesys . impl).<br />
The system <strong>of</strong> medical devices described <strong>in</strong> Section 3.1 is supposed to achieve<br />
that the ventilator mach<strong>in</strong>e is paus<strong>in</strong>g when an X-ray is be<strong>in</strong>g taken, so that the<br />
7 S<strong>in</strong>ce the targeted fragment <strong>of</strong> <strong>AADL</strong> is time-determ<strong>in</strong>istic, our tool has predef<strong>in</strong>ed<br />
the time sampl<strong>in</strong>g strategy to be the maximal strategy that advances time as much<br />
as possible <strong>in</strong> each application <strong>of</strong> the tick rule (see [14] for details).<br />
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30<br />
X-ray is not blurred. The follow<strong>in</strong>g Real-Time Maude time-bounded search comm<strong>and</strong><br />
analyzes this property by check<strong>in</strong>g whether an undesired state, namely<br />
one where the X-ray device thread xmTh is <strong>in</strong> state xray while the ventilator<br />
thread vmTh is not <strong>in</strong> state paused, can be reached from the <strong>in</strong>itial state<br />
{MAIN system Wholesys . impl} <strong>in</strong> less than 4 time units:<br />
Maude> (tsearch<br />
<strong>in</strong>itializeThreads({MAIN system Wholesys . impl}) =>* {C:Configuration}<br />
such that<br />
((location <strong>of</strong> component (MAIN -> XRayMach<strong>in</strong>e -> xmPr -> xmTh)<br />
<strong>in</strong> C:Configuration) == xray<br />
<strong>and</strong><br />
(location <strong>of</strong> component<br />
(MAIN -> VentilatorMach<strong>in</strong>e -> vmPr -> vmTh)<br />
<strong>in</strong> C:Configuration) =/= paused)<br />
<strong>in</strong> time < 4 .)<br />
LTL Model Check<strong>in</strong>g. As already mentioned <strong>in</strong> Section 2.2, Real-Time Maude<br />
is equipped with an explicit-state l<strong>in</strong>ear termporal logic (LTL) model checker<br />
that analyzes whether all behaviors (possibly up to a given duration) from the<br />
<strong>in</strong>itial state satisfy an LTL formula. Aga<strong>in</strong>, we have pre-def<strong>in</strong>ed useful atomic<br />
propositions, such as getBuffer(full port name), getInternalBuffer(full port<br />
name), <strong>and</strong> full thread name @ location. The latter holds when the thread is <strong>in</strong><br />
state location <strong>and</strong> is def<strong>in</strong>ed as follows:<br />
op _@_ : EComponentId Location -> Prop [ctor] .<br />
var SYSTEM : Configuration . var ECI : EComponentId . var L : Location .<br />
eq SYSTEM |= (ECI @ L) = ((location <strong>of</strong> component ECI <strong>in</strong> SYSTEM) == L) .<br />
Example 3. We can use the LTL model checker to analyze two desired properties<br />
<strong>of</strong> our medical system:<br />
1. The ventilation mach<strong>in</strong>e must be paus<strong>in</strong>g when an X-ray is be<strong>in</strong>g taken.<br />
2. S<strong>in</strong>ce the button is pushed at time 0, an X-ray should be taken with<strong>in</strong> three<br />
seconds <strong>of</strong> the start <strong>of</strong> the system.<br />
The first property, which has already been subjected to reachability analysis,<br />
can be model checked by the follow<strong>in</strong>g untimed model check<strong>in</strong>g comm<strong>and</strong>:<br />
Maude> (mc <strong>in</strong>itializeThreads({MAIN system Wholesys . impl}) |=u<br />
[] (((MAIN -> XRayMach<strong>in</strong>e -> xmPr -> xmTh) @ xray)<br />
-><br />
((MAIN -> VentilatorMach<strong>in</strong>e -> vmPr -> vmTh) @ paused)) .)<br />
The second requirement amounts to check<strong>in</strong>g the time-bounded liveness property<br />
that the xmTh thread will always reach its xray state with<strong>in</strong> 3 time units:<br />
Maude> (mc <strong>in</strong>itializeThreads({MAIN system Wholesys . impl}) |=t<br />
((MAIN -> XRayMach<strong>in</strong>e -> xmPr -> xmTh) @ xray) <strong>in</strong> time
Surpris<strong>in</strong>gly, this latter model check<strong>in</strong>g comm<strong>and</strong> returned a counterexample<br />
demonstrat<strong>in</strong>g that the expected property does not hold for all behaviors from<br />
the <strong>in</strong>itial state. Analyz<strong>in</strong>g the counterexample revealed a previously unknown<br />
faulty behavior, where, due to some subtle timer issues, the X-ray mach<strong>in</strong>e th<strong>in</strong>ks<br />
that it has already taken an X-ray even though it is only wait<strong>in</strong>g to take an X-ray.<br />
3.4 The <strong>AADL</strong>2Maude Tool<br />
The above semantics <strong>of</strong> <strong>AADL</strong> has been automated <strong>in</strong> the <strong>AADL</strong>2Maude tool.<br />
<strong>AADL</strong>2Maude is an OSATE plug-<strong>in</strong> that uses OSATE’s code generation facility<br />
to automatically generate Real-Time Maude specifications from <strong>AADL</strong> models.<br />
The executable, formal semantics <strong>of</strong> <strong>AADL</strong> models has been <strong>in</strong>tegrated <strong>in</strong>to<br />
the OSATE environment, enabl<strong>in</strong>g techniques for verify<strong>in</strong>g critical properties<br />
over <strong>AADL</strong> specifications. An <strong>AADL</strong> specification is usually def<strong>in</strong>ed <strong>in</strong> OSATE<br />
<strong>in</strong> either textual or graphical format. The abstract syntax <strong>of</strong> <strong>AADL</strong> <strong>and</strong> <strong>of</strong><br />
its <strong>Behavioral</strong> Annex are def<strong>in</strong>ed as MOF metamodels. OSATE parses <strong>AADL</strong><br />
specifications <strong>and</strong> obta<strong>in</strong>s <strong>AADL</strong> models, which conform to the metamodels<br />
above, that represent their abstract syntax trees.<br />
Our tool adds a model compiler to OSATE as a plug<strong>in</strong> that, given an <strong>AADL</strong><br />
specification, automatically generates a formal, executable, Real-Time Maude<br />
model correspond<strong>in</strong>g exactly to its rewrt<strong>in</strong>g logic semantics. This is obta<strong>in</strong>ed by<br />
means <strong>of</strong> the function mapp<strong>in</strong>g the model M<strong>AADL</strong> to a real-time rewrite theory<br />
M<strong>AADL</strong>. The function has been implemented us<strong>in</strong>g OSATE’s traversal<br />
mechanisms mapp<strong>in</strong>g each object <strong>in</strong> an <strong>AADL</strong> model to an element <strong>of</strong> a Real-<br />
Time Maude theory as expla<strong>in</strong>ed <strong>in</strong> Section 3.2. Our approach allows an <strong>AADL</strong><br />
modeler to work with <strong>AADL</strong> models as mathematical entities with<strong>in</strong> the OSATE<br />
environment itself, thus enhanc<strong>in</strong>g the application <strong>of</strong> the analysis techniques supported<br />
<strong>in</strong> Real-Time Maude.<br />
4 An Active St<strong>and</strong>by System Example<br />
In order to further illustrate how <strong>AADL</strong> design can benefit from Maude-based<br />
formal analysis us<strong>in</strong>g the <strong>AADL</strong>2Maude tool cha<strong>in</strong>, we give an overview <strong>of</strong> the<br />
verification <strong>of</strong> another example, an Active St<strong>and</strong>by system for decid<strong>in</strong>g which<br />
<strong>of</strong> two computer systems is active <strong>in</strong> an aircraft. This model is an <strong>AADL</strong> variant<br />
developed by Abdullah Al-Nayeem <strong>of</strong> a similar active st<strong>and</strong>by specification<br />
by Steve Miller <strong>and</strong> Darren C<strong>of</strong>er from Rockwell-Coll<strong>in</strong>s. This example <strong>and</strong> its<br />
properties is also discussed <strong>in</strong> [11].<br />
4.1 The Active St<strong>and</strong>by System<br />
The Active St<strong>and</strong>by system is a simplified example <strong>of</strong> a fault-tolerant Avionics<br />
system. In <strong>in</strong>tegrated modular avionics (IMA), a cab<strong>in</strong>et is a chassis with a power<br />
supply, <strong>in</strong>ternal bus, <strong>and</strong> general purpose comput<strong>in</strong>g, I/O, <strong>and</strong> memory cards.<br />
Aircraft applications are implemented us<strong>in</strong>g the resources <strong>in</strong> the cab<strong>in</strong>ets. There<br />
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32<br />
are always two or more cab<strong>in</strong>ets that are physically separated on the aircraft so<br />
that physical damage (e.g., an explosion) doesn’t take out the computer system.<br />
The Active St<strong>and</strong>by system considers the case <strong>of</strong> two cab<strong>in</strong>ets <strong>and</strong> focuses on<br />
the logic <strong>of</strong> decid<strong>in</strong>g which side is active. While one side is active, the other side<br />
rema<strong>in</strong>s passive. The two sides receive <strong>in</strong>puts through communication channels.<br />
Each side could fail, but it is assumed that both sides cannot fail at the same<br />
time. A failed side can recover after failure. In case one side fails, the nonfailed<br />
side should be the active side. In addition, the user/pilot can toggle the<br />
active status <strong>of</strong> these sides. Each side is dependent on other system components.<br />
In this example, the full functionality <strong>of</strong> each side is dependent on these two<br />
sides’ perception <strong>of</strong> the availability <strong>of</strong> these system components. Only a fully<br />
functional/available side should be active, while the other side is alive but not<br />
fully functional. Each side monitors the status <strong>of</strong> other side <strong>and</strong> acts upon the<br />
monitored result.<br />
Important properties that the Active St<strong>and</strong>by system should satisfy <strong>in</strong>clude:<br />
R1: Both sides should agree on which side is active (provided neither side has<br />
failed, the availability <strong>of</strong> a side has not changed, <strong>and</strong> the pilot has not made<br />
a manual selection).<br />
R2: A side that is not fully available should not be the active side if the other<br />
side is fully available (aga<strong>in</strong>, provided neither side has failed, the availability<br />
<strong>of</strong> a side has not changed, <strong>and</strong> the pilot has not made a manual selection).<br />
R3: The pilot can always change the active side (except if a side is failed or the<br />
availability <strong>of</strong> a side has changed).<br />
R4: If a side is failed the other side should become active.<br />
R5: The active side should not change unless the availability <strong>of</strong> a side changes,<br />
the failed status <strong>of</strong> a side changes, or manual selection is selected by the<br />
pilot.<br />
4.2 <strong>AADL</strong> Model <strong>of</strong> the Active St<strong>and</strong>by System<br />
As already mentioned, the Active St<strong>and</strong>by system has been modeled <strong>in</strong> <strong>AADL</strong><br />
by Abdullah Al-Nayeem. The architecture <strong>of</strong> the system is shown <strong>in</strong> Figure 1.<br />
The top-level system specification consists <strong>of</strong> three <strong>AADL</strong> system components:<br />
Side1, Side2, <strong>and</strong> Environment. Side1 <strong>and</strong> Side2 encapsulate the behaviors <strong>of</strong><br />
the two sides. The Environment component can be considered as an abstract<br />
representation <strong>of</strong> other non-specified components that <strong>in</strong>teract with Side1 <strong>and</strong><br />
Side2. The behavior <strong>of</strong> each component is def<strong>in</strong>ed by a periodic thread.<br />
The <strong>AADL</strong> design <strong>of</strong> the Active St<strong>and</strong>by system is globally synchronous;<br />
i.e., all threads <strong>in</strong>side Side1, Side2, <strong>and</strong> Environment have the same period <strong>and</strong><br />
dispatch at the same time. These three components are wrapped <strong>in</strong> a system<br />
component ActiveSt<strong>and</strong>bySystem.<br />
Each time the thread <strong>in</strong>side Environment dispatches, it sends 5 boolean values,<br />
one through each <strong>of</strong> its out ports shown <strong>in</strong> Figure 1. These values are<br />
nondeterm<strong>in</strong>istically generated, with the constra<strong>in</strong>ts that two sides cannot fail
side1Failed<br />
Side1<br />
side1FullyAvail<br />
Environment<br />
manualSelection<br />
side1ActiveSide<br />
mon1Side1FullyAvail<br />
mon1Side2FullyAvail<br />
side2ActiveSide<br />
mon2Side1FullyAvail<br />
mon2Side2FullyAvail<br />
side2FullyAvail<br />
Side2<br />
Fig. 1. Architecture <strong>of</strong> the Active St<strong>and</strong>by system <strong>in</strong> <strong>AADL</strong><br />
side2Failed<br />
at the same time, <strong>and</strong> that the failed side cannot be fully available. These assumptions<br />
are specified <strong>in</strong> <strong>AADL</strong> as a value constra<strong>in</strong>t property <strong>in</strong> the thread<br />
<strong>in</strong>side Environment:<br />
PalsProperties::ValueConstra<strong>in</strong>ts =><br />
"not s1F <strong>and</strong> s2F <strong>and</strong> not s2FA or not s2F <strong>and</strong><br />
s1F <strong>and</strong> not s1FA or not s1F <strong>and</strong> not s2F";<br />
4.3 Apply<strong>in</strong>g the PALS Philosophy to the Active St<strong>and</strong>by <strong>AADL</strong><br />
Model<br />
The above-described <strong>AADL</strong> model <strong>of</strong> the active st<strong>and</strong>by system is not really<br />
synchronous. It is <strong>in</strong>stead an asynchronous model. This is due to semantics<br />
<strong>of</strong> <strong>AADL</strong> models, s<strong>in</strong>ce <strong>in</strong> an <strong>AADL</strong> model consist<strong>in</strong>g <strong>of</strong> several threads, each<br />
<strong>in</strong>dividual thread can perform transitions on its own, lead<strong>in</strong>g to an asynchronous<br />
<strong>and</strong> highly concurrent behavior, <strong>and</strong> therefore to a big state space explosion.<br />
Therefore, <strong>in</strong> a sense the <strong>AADL</strong> model <strong>of</strong> the active st<strong>and</strong>by system is halfway<br />
between the <strong>in</strong>tended synchronous system <strong>and</strong> the <strong>AADL</strong> model result<strong>in</strong>g from<br />
apply<strong>in</strong>g the PALS pattern, which is even more complex <strong>and</strong> <strong>of</strong> course also<br />
asynchronus.<br />
In our own experiments model check<strong>in</strong>g the above, really asynchronous model,<br />
we run <strong>in</strong>to a performance barrier both <strong>in</strong> time <strong>and</strong> space. It was possible to perform<br />
bounded model check<strong>in</strong>g analyses <strong>of</strong> the model for modest depth bounds,<br />
33
34<br />
but full model check<strong>in</strong>g analysis was unfeasible. As a sanity check, we also specified<br />
directly <strong>in</strong> Real-Time Maude a, still asynchronous, version <strong>of</strong> the active<br />
st<strong>and</strong>by system. We were able to fully verify all the safety requirements <strong>of</strong> this<br />
Real-Time Maude model <strong>in</strong> less than a m<strong>in</strong>ute. The difference with the performance<br />
barriers for the similar <strong>AADL</strong> version <strong>of</strong> the model was that, <strong>in</strong> addition<br />
to the asynchrony shared by both models, the <strong>AADL</strong> model (<strong>and</strong> therefore also<br />
its Real-Time Maude translation) was considerably more complex, with the size<br />
<strong>of</strong> a s<strong>in</strong>gle <strong>AADL</strong> model state occupy<strong>in</strong>g about six pr<strong>in</strong>ted pages. In reality,<br />
each component is not just a s<strong>in</strong>gle object, but a relatively large collection <strong>of</strong><br />
concurrent objects; s<strong>in</strong>ce each <strong>of</strong> its gates is itself a nontrivial object conta<strong>in</strong><strong>in</strong>g<br />
a buffer <strong>and</strong> additional state <strong>in</strong>formation.<br />
All this means that we were really analyz<strong>in</strong>g the wrong model to beg<strong>in</strong> with,<br />
because we were not tak<strong>in</strong>g advantage <strong>of</strong> the PALS methodology [11, 9]. Specifically,<br />
as expla<strong>in</strong>ed <strong>in</strong> detail <strong>in</strong> [9], the PALS transformation applies to any<br />
ensemble E <strong>of</strong> state mach<strong>in</strong>es connected by a wir<strong>in</strong>g diagram so that: (i) the<br />
s<strong>in</strong>gle state mach<strong>in</strong>e obta<strong>in</strong>ed as the synchronous composition <strong>of</strong> E, <strong>and</strong> (ii) the<br />
asynchronous system obta<strong>in</strong>ed by apply<strong>in</strong>g to E the PALS transformation (for<br />
given parameters <strong>of</strong> clock skew, local transition times, <strong>and</strong> maximum network<br />
delay) are <strong>in</strong> fact bisimilar. In particular, both system saisfy the same temporal<br />
logic properties [9], but is <strong>of</strong> course much easier to model check the synchronous<br />
composition, while it is typically unfeasible to model check the correspond<strong>in</strong>g<br />
PALS-transformed system. This means that the right <strong>AADL</strong> model to analyze<br />
for a given ensemble E is not its natural asynchronous version, where each mach<strong>in</strong>e<br />
<strong>in</strong> E can perform transitions on its own, but <strong>in</strong>stead the <strong>AADL</strong> model <strong>of</strong><br />
its synchronous composition.<br />
For the active st<strong>and</strong>by example, what this means is that we should specify the<br />
<strong>AADL</strong> model correspond<strong>in</strong>g to such a synchronous composition. This is exactly<br />
what we did, allow<strong>in</strong>g us to model check all the desired safety properties <strong>in</strong> a<br />
few m<strong>in</strong>utes as expla<strong>in</strong>ed <strong>in</strong> what follows.<br />
4.4 <strong>Formal</strong> <strong>Analysis</strong> <strong>of</strong> the Synchronous <strong>AADL</strong> Model<br />
Tak<strong>in</strong>g the synchronous model <strong>of</strong> the Active St<strong>and</strong>by system <strong>in</strong> <strong>AADL</strong> as <strong>in</strong>put,<br />
the <strong>AADL</strong>2Maude tool cha<strong>in</strong> automatically generates the correspond<strong>in</strong>g Real-<br />
Time Maude specification, a timed object-oriented module ACTIVE-STANDBY--<br />
SYSTEM. Then the safety requirements for the Active St<strong>and</strong>by system are specified<br />
<strong>and</strong> model checked <strong>in</strong> the MODEL-CHECK-ACTIVE-STANDBY module, which<br />
also def<strong>in</strong>es the <strong>in</strong>itial state <strong>in</strong>it:<br />
(tomod MODEL-CHECK-ACTIVE-STANDBY is<br />
<strong>in</strong>clud<strong>in</strong>g <strong>AADL</strong>-MODEL-CHECKER .<br />
<strong>in</strong>clud<strong>in</strong>g ACTIVE-STANDBY-SYSTEM .<br />
op <strong>in</strong>it : -> GlobalSystem .<br />
eq <strong>in</strong>it = <strong>in</strong>itializeThreads{MAIN system ActiveSt<strong>and</strong>bySystem . impl} .<br />
......<br />
endtom)
We use temporal logic formulae to encode requirements R1 to R5. Due to the<br />
globally synchronous design <strong>of</strong> Active St<strong>and</strong>by, we restrict our attention to the<br />
stable state <strong>in</strong> each period. A state is stable if it is at the moment <strong>of</strong> dispatch.<br />
The notion <strong>of</strong> a stable state is def<strong>in</strong>ed as an atomic proposition stable.<br />
We likewise def<strong>in</strong>e the exact mean<strong>in</strong>g <strong>of</strong> specialized words like active, failed,<br />
<strong>and</strong> changed as atomic propositions. For example, the atomic proposition side1-<br />
FullyAvailNow holds if <strong>and</strong> only if <strong>in</strong> the thread <strong>of</strong> Side1, the received message<br />
stored <strong>in</strong> the <strong>in</strong>ternal buffer <strong>of</strong> the <strong>in</strong> port side1FullyAvail has value true:<br />
var CONF : Configuration . var B : Bool .<br />
ceq {CONF} |= side1FullyAvailNow = B<br />
if B := boolFromPort(<br />
MAIN -> sidesOneTwo -> sideProcess -><br />
sideThread -> side1FullyAvail, Conf ) .<br />
ceq {CONF} |= side2FullyAvailNow = B<br />
if B := boolFromPort(<br />
MAIN -> sidesOneTwo -> sideProcess -><br />
SideThread -> side2FullyAvail, Conf ) .<br />
We comb<strong>in</strong>e atomic propositions <strong>in</strong>to more complex LTL formulae, such as<br />
NoChangeAssumption, which def<strong>in</strong>es the conditions under which both R1 <strong>and</strong><br />
R2 must hold:<br />
op NoChangeAssumption : -> Prop .<br />
eq NoChangeAssumption =<br />
(Side1FullyAvailNow /\ Side2FullyAvailNow /\ NoChangeInAvailability /\<br />
NoManualSelectionPressed /\ NeitherSideFailed /\ NeitherSideFailedNow) .<br />
A more precise def<strong>in</strong>ition <strong>of</strong> requirement R1 is that, <strong>in</strong> a stable state where<br />
no assumptions are changed, both sides must agree on active side either <strong>in</strong> the<br />
current state or <strong>in</strong> the next stable state. This requirement can be formalized as<br />
the follow<strong>in</strong>g temporal logic formula R1:<br />
op R1 : -> Formula .<br />
eq R1 = [] ((NoChangeAssumption /\ Stable)<br />
-> (AgreeOnActiveSide<br />
\/ O ((~ Stable) U (Stable /\ AgreeOnActiveSide)))<br />
S<strong>in</strong>ce the <strong>AADL</strong>2Maude tool cha<strong>in</strong> automatically generates a Real-Time<br />
Maude translation <strong>of</strong> an <strong>AADL</strong> model, we could <strong>in</strong>ject formal analysis <strong>in</strong>to<br />
the <strong>AADL</strong> design process <strong>of</strong> Active St<strong>and</strong>by. Indeed, the synchronous Active<br />
St<strong>and</strong>by system satisfies all five requirements, as shown by the follow<strong>in</strong>g model<br />
check<strong>in</strong>g comm<strong>and</strong>, which took about six m<strong>in</strong>utes to execute:<br />
(mc <strong>in</strong>it |=u (R1 /\ R2 /\ R3 /\ R4 /\ R5) .)<br />
35
36<br />
rewrites: 277333182 <strong>in</strong> 373655ms cpu (375661ms real) (742216 rewrites/second)<br />
Result Bool :<br />
true<br />
This <strong>of</strong> course means that the <strong>AADL</strong> model for the PALS-transformed version<br />
<strong>of</strong> this synchronous model <strong>of</strong> the active st<strong>and</strong>by system will also satisfy the same<br />
safety requirements, even though it is unfeasible to verify this fact directly by<br />
model check<strong>in</strong>g on the much more complex PALS-transformed version.<br />
5 Related Work<br />
The applications <strong>of</strong> formal methods to analyze <strong>AADL</strong> models can be divided<br />
<strong>in</strong>to two classes: analyz<strong>in</strong>g schedulability <strong>of</strong> an architectural subset <strong>of</strong> <strong>AADL</strong><br />
where thread behavior is only characterized by dispatch protocol <strong>and</strong> execution<br />
time [17, 6], <strong>and</strong> analyz<strong>in</strong>g behaviors <strong>in</strong> behavioral subsets <strong>of</strong> <strong>AADL</strong> similar to<br />
the one chosen <strong>in</strong> our work.<br />
For analyz<strong>in</strong>g behaviors <strong>of</strong> <strong>AADL</strong> models, the work reported <strong>in</strong> [2] is the<br />
closest to ours. As similar subset <strong>of</strong> <strong>AADL</strong> is translated <strong>in</strong>to an extension <strong>of</strong><br />
Petri nets. Their model checker selt can then be used to analyze abstractions<br />
<strong>of</strong> <strong>AADL</strong> models, <strong>in</strong>clud<strong>in</strong>g their LTL properties. However, the paper does not<br />
expla<strong>in</strong> their semantics. The paper [7] also covers a similar subset <strong>of</strong> <strong>AADL</strong>,<br />
except that thread behavior is not given by the behavioral annex, but is <strong>in</strong>stead<br />
given as a program <strong>in</strong> the synchronous language Lustre. In [1], the authors translate<br />
a behavioral subset, m<strong>in</strong>us mode switches, to IF, where they can analyze<br />
safety properties <strong>of</strong> the system. The behaviors are, however, not expressed us<strong>in</strong>g<br />
<strong>AADL</strong>’s behavioral annex, but their own behavioral language. In [18], a smaller<br />
subset (periodic threads, no modes) is translated to timed abstract state mach<strong>in</strong>es,<br />
<strong>and</strong> model check<strong>in</strong>g <strong>in</strong> the timed automaton tool Uppaal is suggested<br />
to verify tim<strong>in</strong>g properties.<br />
6 Conclusions<br />
<strong>AADL</strong>’s current lacks <strong>of</strong> a formal semantics <strong>and</strong> <strong>of</strong> executability are two severe<br />
limitations, particularly for certifiable safety-critical embedded systems. In this<br />
work we solve these two problems for a substantial subset <strong>of</strong> <strong>AADL</strong> by provid<strong>in</strong>g<br />
a formal rewrit<strong>in</strong>g semantics <strong>of</strong> it <strong>in</strong> Real-Time Maude, <strong>and</strong> by deriv<strong>in</strong>g<br />
from this semantics a tool, <strong>AADL</strong>2Maude, that connects the OSATE <strong>AADL</strong> tool<br />
with Real-Time Maude <strong>and</strong> supports simulation, reachability, <strong>and</strong> LTL model<br />
check<strong>in</strong>g analyses <strong>of</strong> <strong>AADL</strong> models <strong>in</strong> this subset. Furthermore, we have illustrated<br />
the use <strong>of</strong> <strong>AADL</strong>2Maude with two case studies, one <strong>of</strong> safe medical device<br />
<strong>in</strong>teroperation, <strong>and</strong> another on safety <strong>of</strong> an avionics system.<br />
Our experience is quite encourag<strong>in</strong>g, but much work rema<strong>in</strong>s ahead. Increas<strong>in</strong>gly<br />
larger <strong>AADL</strong> subsets should be given a formal rewrit<strong>in</strong>g logic semantics to<br />
achieve the goal <strong>of</strong> giv<strong>in</strong>g a formal semantics to the entire <strong>AADL</strong> st<strong>and</strong>ard <strong>and</strong>
hav<strong>in</strong>g simulation <strong>and</strong> formal analysis tools for <strong>AADL</strong> based on such a semantics.<br />
Also, further experimentation to extend <strong>and</strong> perfect our approach should<br />
be carried out. We also plan to extend the facilities described <strong>in</strong> this paper to<br />
make it easy for users to specify formal properties <strong>of</strong> <strong>AADL</strong> models <strong>in</strong>to an<br />
<strong>AADL</strong> “formal property annex,” so that such properties can be expressed solely<br />
<strong>in</strong> terms <strong>of</strong> the given <strong>AADL</strong> model.<br />
References<br />
1. Abdoul, T., Champeau, J., Dhaussy, P., Pilla<strong>in</strong>, P.Y., Roger, J.C.: <strong>AADL</strong> execution<br />
semantics transformation for formal verification. In: ICECCS’08. IEEE (2008)<br />
2. Berthomieu, B., Bodeveix, J.P., Chaudet, C., Dal-Zilio, S., Filali, M., Vernadat,<br />
F.: <strong>Formal</strong> verification <strong>of</strong> <strong>AADL</strong> specifications <strong>in</strong> the Topcased environment. In:<br />
Ada-Europe’09. LNCS, vol. 5570. Spr<strong>in</strong>ger (2009)<br />
3. Clavel, M., Durán, F., Eker, S., L<strong>in</strong>coln, P., Martí-Oliet, N., Meseguer, J., Talcott,<br />
C.: Maude Manual (Version 2.3) (January 2007), http://maude.cs.uiuc.edu<br />
4. Clavel, M., Durán, F., Eker, S., L<strong>in</strong>coln, P., Mart-Oliet, N., Meseguer, J., Talcott,<br />
C.: All About Maude - A High-Performance Logical Framework, LNCS, vol. 4350.<br />
Spr<strong>in</strong>ger (2007)<br />
5. França, R., Bodeveix, J.P., Filali, M., Roll<strong>and</strong>, J.F., Chemouil, D., Thomas, D.:<br />
The <strong>AADL</strong> behaviour annex - experiments <strong>and</strong> roadmap. In: ICECCS. IEEE (2007)<br />
6. Gui, S., Luo, L., Li, Y., Wang, L.: <strong>Formal</strong> schedulability analysis <strong>and</strong> simulation<br />
for <strong>AADL</strong>. In: ICESS’08. IEEE (2008)<br />
7. Jahier, E., Halbwachs, N., Raymond, P., Nicoll<strong>in</strong>, X., Lesens, D.: Virtual execution<br />
<strong>of</strong> <strong>AADL</strong> models via a translation <strong>in</strong>to synchronous programs. In: Proc.<br />
EMSOFT’07. ACM (2007)<br />
8. Meseguer, J.: Membership algebra as a logical framework for equational specification.<br />
In: Parisi-Presicce, F. (ed.) Proc. WADT’97. LNCS, vol. 1376, pp. 18–61.<br />
Spr<strong>in</strong>ger (1998)<br />
9. Meseguer, J., Ölveczky, P.C.: <strong>Formal</strong>ization <strong>and</strong> correctness <strong>of</strong> the PALS pattern<br />
for asynchronous real-time systems. Tech. rep., CS Dept. University <strong>of</strong><br />
Ill<strong>in</strong>ois at Urbana-Champaign (2009), cS Tech. Rep. 2009-11-12. Available at<br />
https://www.ideals.ill<strong>in</strong>ois.edu/h<strong>and</strong>le/2142/10762<br />
10. Meseguer, J., Talcott, C.: Semantic models for distributed object reflection. In:<br />
Proceed<strong>in</strong>gs <strong>of</strong> ECOOP’02, Málaga, Spa<strong>in</strong>, June 2002. pp. 1–36. Spr<strong>in</strong>ger LNCS<br />
2374 (2002)<br />
11. Miller, S., C<strong>of</strong>er, D., Sha, L., Meseguer, J., Al-Nayeem, A.: Implement<strong>in</strong>g logical<br />
synchrony <strong>in</strong> <strong>in</strong>tegrated modular avionics. In: Proc. 28th Digital Avionics Systems<br />
Conference. IEEE (2009)<br />
12. Ölveczky, P.C., Meseguer, J.: Specification <strong>of</strong> real-time <strong>and</strong> hybrid systems <strong>in</strong><br />
rewrit<strong>in</strong>g logic. Theoretical Computer Science 285, 359–405 (2002)<br />
13. Ölveczky, P.C., Meseguer, J.: Abstraction <strong>and</strong> completeness for Real-Time Maude.<br />
Electronic Notes <strong>in</strong> Theoretical Computer Science 176(4), 5–27 (2007)<br />
14. Ölveczky, P.C., Meseguer, J.: <strong>Semantics</strong> <strong>and</strong> pragmatics <strong>of</strong> Real-Time Maude.<br />
Higher-Order <strong>and</strong> Symbolic Computation 20(1-2), 161–196 (2007)<br />
15. SAE <strong>AADL</strong> Team: <strong>AADL</strong> homepage (2009), http://www.aadl.<strong>in</strong>fo/<br />
16. SEA: Architecture <strong>Analysis</strong> & Design Language (<strong>AADL</strong>). AS5506A, Version 2.0,<br />
SAE Aerospace (2009), http://www.sae.org/technical/st<strong>and</strong>ards/AS5506A<br />
37
38<br />
17. Sokolsky, O., Lee, I., Clarke, D.: Schedulability analysis <strong>of</strong> <strong>AADL</strong> models. In: Proc.<br />
IPDPS’06. IEEE (2006)<br />
18. Yang, Z., Hu, K., Ma, D., Pi, L.: Towards a formal semantics for the <strong>AADL</strong> behavior<br />
annex. In: Proc. DATE’09. IEEE (2009)