Ultra fast ADC - University of Cambridge

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LAB : Laboratoire d’Astrophysique de Bordeaux • Ultra fast ADC: 8GS/s 3-bit ADC (65nm CMOS techn.) – The outputs speed rate is too high (2GS/s) to capture the synchronous digital data with standard FPGA ⇒ External DMUX circuits are needed to use this ultra fast ADC ⇒ Total power consumption increases (>3W) Internal DMUX DMUX AAVP workshop 8-10 December 2010, University Of Cambridge
LAB : Laboratoire d’Astrophysique de Bordeaux • Ultra fast ADC: Future design in 65nm CMOS Technology – In 2011, a new 8GS/s Track and Hold circuit will be designed to improve the linearity in order to obtain an ENOB superior to 6 bits. – This new Track and Hold circuit will be: designed with 65nm CMOS technology from STm. used in a new ultra fast ADC. • A 8GS/s 6-bit flash ADC (2012): prototype version in which will be implemented Calibration circuit to compensate the comparator offsets deviation due to the small size of the NMOS transistor Add scrambler circuit to mix a pseudo random pattern to digital data in order to capture ADC outputs using high speed receivers of standard FPGA (6.5GS/s) ⇒ Internal 1:4 DMUX will be replaced by 1:2 DMUX ⇒ No need of external DMUX Chip-On-Board • A 8GS/s 6-bit flash ADC (2013): Final version Packaged version (fcBGA) AAVP workshop 8-10 December 2010, University Of Cambridge
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Ultra fast ADC - University of Cambridge

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