Ultra fast ADC - University of Cambridge

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LAB : Laboratoire d’Astrophysique de Bordeaux • AAVP Context: what could be done – Design an ADC for AAVP program Folding Architecture Number of comparator: Full Flash ADC: 2N-1 Folding ADC: ≈(2N-1)/2 3-bit flash ADC ⇒ 7 comparators 3-bit folding ADC ⇒ 3 comparators The folding architecture seems to be the most relevant for AAVP AAVP workshop 8-10 December 2010, University Of Cambridge
LAB : Laboratoire d’Astrophysique de Bordeaux • AAVP Context: what could be done – Design an ADC for AAVP program Which ADC architecture is suitable for AAVP program? • If the flash architecture is replaced by folding architecture, the power consumption of ADC can be reduced by about 30% • Folding ⇒ state-of-the-art in 45nm CMOS technology « Design of a 12.5GS/s 5-bit folding A/D converter », Surano, 2009: analog BW: 6GHz, power consumption: 53mW (simulated result) The design of a low power 3GS/s 6-bit ADC using a flash folding architecture is possible with 65nm CMOS technology LAB has access to the 65nm CMOS technology from STm The design of an ADC for AAVP could be included in our roadmap Funding: For design: 200k€ is needed to design such ADC: 3 FTE + 2 foundry runs (prototype and final version) For production: wafer cost: >250k€ (to be confirmed), depends on the number of ADC needed AAVP workshop 8-10 December 2010, University Of Cambridge
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Ultra fast ADC - University of Cambridge

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