Ultra fast ADC - University of Cambridge

LAB : Laboratoire d’Astrophysique de Bordeaux 

Fast Analog to Digital Converter 

Developments 

Stephane GAUFFRE, Philippe CAÏS, Benjamin Quertier 

Laboratoire d’Astrophysique de Bordeaux 

AAVP workshop 8-10 December 2010, University Of Cambridge


Outline 

ADC designed by LAB 

Herschel 

ALMA 

Ultra fast ADC 

Current Design 

Future Design 

AAVP context 

Low Power ADC 



• ADC designed by LAB: 

– Flash architecture used for our applications. 

Ultra fast ADC (>1GS/s) 

Large analog bandwith (≥1 octave) 

Low resolution (≤6-bit) 



• ADC designed by LAB: Herschel Space Observatory (HiFi) 

– Cooperation between three groups from Bordeaux (LAB, IMS) and Toulouse 

(CESR), 2002 

– 2-bit ADC at 500MS/s designed in 0.8µm BiCMOS Technology from AMS for ESA 

space program (HSO). 

– Flash architecture 

– Power consumption: ≈280mW 



• ADC designed by LAB: ALMA 

2-4 GHz 

4 GHz 

0 dBm 

– Cooperation between two groups from Bordeaux (LAB, IMS), 2005 

– 3-bit ADC at 4GS/s designed in 0.25µm SiGe BiCMOS Technology from STm 

– Flash architecture 

– Power consumption: ≈1.45W 

VH 

Amplifier 

VL 

OTA 

Bandgap 

Adaptater 

amplifier 

Clock 

buffer 

+ 

- 

+ 

- 

+ 

- 

+ 

- 

+ 

- 

+ 

- 

+ 

- 

D 

D 

D 

D 

D D 

D 

D 

D 

D 

D 

D 

D 

D 

FDL 

encoder 

D-Latch 

D-Latch 

D-Latch 

Output 

buffer 

Output 

buffer 

Output 

buffer 

AAVP workshop 8-10 December 2010, University Of Cambridge 

D0 

D1 

D2


• ADC designed by LAB: ALMA 

– The 4GS/s 3-bit ADC runs with 3 1:16 DMUX circuits designed by LAB with STm 

0.25µm SiGe BiCMOS technology. 

– Total power consumption: 1.45+0.7×3=3.55W (power supply at 2.5V) 

– Wafers specialy manufactured for the ALMA project (>800 sampler chips and 

>2000 DMUX chips) 

– Around 300 Digitizer modules assembled, tested and validated to equip 66 

antennas 



• Ultra fast ADC: 

– To design an ultra fast ADC, we must find a finer technology. 

– We can have access to the 65nm CMOS technology from STm via the broker in 

IC, the CMP. 

⇒ multi-projects wafer 

– Ft=210GHz 

⇒ high speed component 

– CMOS tech. & Power supply=1.2V 

⇒ low power consumption 



• Ultra fast ADC: Track And Hold Circuit (65nm CMOS techn.) 

– Cooperation between three groups from Bordeaux (LAB, IMS, CENBG), 2010 

– 8GS/s Track and Hold circuit with an analog bandwith of 7.5GHz (0.5-8GHz) 

– Designed with 65nm CMOS technology from STm 

– ENOB≈4.5bit, Input Refllexion


• Ultra fast ADC: 8GS/s 3-bit ADC (65nm CMOS techn.) 

– 8GS/s 3-bit flash ADC with an analog bandwith of 8GHz and internal 1:4 DMUX. 

– Designed with 65nm CMOS technology from STm 

– Chip-On-Board 

– Power consumption: ≈500mW (simulated result) 

⇒ The layout drawing files were sent to STm foundry last week. 




– The outputs speed rate is too high (2GS/s) to capture the synchronous digital data 

with standard FPGA 

⇒ External DMUX circuits are needed to use this ultra fast ADC 

⇒ Total power consumption increases (>3W) 

Internal 

DMUX DMUX 



• Ultra fast ADC: Future design in 65nm CMOS Technology 

– In 2011, a new 8GS/s Track and Hold circuit will be designed to improve the 

linearity in order to obtain an ENOB superior to 6 bits. 

– This new Track and Hold circuit will be: 

designed with 65nm CMOS technology from STm. 

used in a new ultra fast ADC. 

• A 8GS/s 6-bit flash ADC (2012): prototype version in which will be 

implemented 

Calibration circuit to compensate the comparator offsets deviation 

due to the small size of the NMOS transistor 

Add scrambler circuit to mix a pseudo random pattern to digital 

data in order to capture ADC outputs using high speed receivers of 

standard FPGA (6.5GS/s) 

⇒ Internal 1:4 DMUX will be replaced by 1:2 DMUX 

⇒ No need of external DMUX 

Chip-On-Board 

• A 8GS/s 6-bit flash ADC (2013): Final version 

Packaged version (fcBGA) 




– Rough estimation of power consumption if 6-bit designed with the same flash 

architecture as 3-bit ADC (with scrambler circuit and internal1:2 DMUX circuits) 

Power in mW 

1750 

1500 

1250 

1000 

750 

500 

250 

0 

2 3 4 5 6 7 

Resolution (Number of bit) 



• AAVP Context 

– ADC technical parameter requirements: 

Resolution : 4-6bit 

Sample rate: ≥3GS/s 

Bandwith: 

• AA-lo: 70MHz to 450MHz 

• AA-mid: 400MHz to 1.4GHz 

Power:


• AAVP Context: what could be done 

– Design an ADC for AAVP program 

Which ADC architecture is suitable for AAVP program? 

• Sampling rate: The flash achitecture is the fastest 

• Low power ⇒ state-of-the-art in 65nm CMOS technology 

« A 6-bit 5GS/s Nyquist A/D converter in 65nm CMOS 

technology », Choi, June 2008: flash architecture, analog BW: 

2.5GHz, power consumption: 320mW 

• The design of a low power 3GS/s 6-bit flash ADC is possible with the 

65nm CMOS technology. 






• Folding architecture? 





Folding Architecture Number of comparator: 

Full Flash ADC: 2N-1 Folding ADC: ≈(2N-1)/2 3-bit flash ADC 

⇒ 7 comparators 

3-bit folding ADC 

⇒ 3 comparators 

The folding architecture 

seems to be the most relevant 

for AAVP 






• If the flash architecture is replaced by folding architecture, the power 

consumption of ADC can be reduced by about 30% 

• Folding ⇒ state-of-the-art in 45nm CMOS technology 

« Design of a 12.5GS/s 5-bit folding A/D converter », Surano, 2009: 

analog BW: 6GHz, power consumption: 53mW (simulated result) 

The design of a low power 3GS/s 6-bit ADC using a flash folding architecture 

is possible with 65nm CMOS technology 

LAB has access to the 65nm CMOS technology from STm 

The design of an ADC for AAVP could be included in our roadmap 

Funding: 

For design: 200k€ is needed to design such ADC: 3 FTE + 2 foundry 

runs (prototype and final version) 

For production: wafer cost: >250k€ (to be confirmed), depends on the 

number of ADC needed 



Thank you for 

your 

ATTENTION

Ultra fast ADC - University of Cambridge

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