Ultra fast ADC - University of Cambridge

LAB : Laboratoire d’Astrophysique de Bordeaux
• AAVP Context: what could be done
– Design an ADC for AAVP program
Which ADC architecture is suitable for AAVP program?
• Sampling rate: The flash achitecture is the fastest
• Low power ⇒ state-of-the-art in 65nm CMOS technology
« A 6-bit 5GS/s Nyquist A/D converter in 65nm CMOS
technology », Choi, June 2008: flash architecture, analog BW:
2.5GHz, power consumption: 320mW
• The design of a low power 3GS/s 6-bit flash ADC is possible with the
65nm CMOS technology.
AAVP workshop 8-10 December 2010, University Of Cambridge