Chapter 2 THE GENERAL INSTRUMENT CP1600 - Intellivision Brasil

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TYPE STACK INTERRUPT STATUS MNEMONIC PSHR PULR SIN EIS DIS TCI JE JD JSRE JSRD GSWD RSWD CLRC SETC NOPP NOP HLT SDBD OPERAND(S) RS RD (2) LABEL LABEL RB, LABEL RB, LABEL RD RS (2) Table 2-2. <strong>CP1600</strong> Instruct Set Summary (Continued) WORDS 1 1 1 1 1 1 3 3 3 3 1 1 1 1 2 1 1 1 STATUSES S Z C O X X X X 0 1 Separate mnemonics for MVO@ RS,R6 Seperate mnemonics for MVI@ R6,RD PCIT ¬ Softwate interrupt OPERATION PERFORMED Enable interrupt system. Disable interupt system. Terminate current interrupt. Jump to given address and enble interrupt system. Jump to give address and disable interrupt system. Jump to given address, saving Program Counter in R4, R5, or R6, and enable interrupt system. Jump to given address, saving Program Counter in R4, R5, or R6, and disable interrupt system. [RD ] ¬ [SW]; [RD] ¬ [SW] Place Status Word in upper half of each byte of the specified register. RD may be R0, R1, R2, or R3. [SW] ¬ [RS] Load Status Word from bits 7 through 4 of the specified register. [C] ¬ 0 Clear Carry. [C] ¬ 1 Set Carry. No Operation Halt after executing next instruction. Set double byt data mode for next instruction, which mush be one of the following types: Primary or secondary I/O or memory reference Immediate or immediate operate If implied addressing throught R1, R2, or R3 is used, the same byte will be accessed twice; addressing through R4, R5, or R7 will give bytes from the addressed location and that addressed after auto-increment. Direct addressing and Stack addressing are not allowed in double byte mode.
The following notation is used in Table 2-4: Table 2-3. <strong>CP1600</strong> Branch Conditions and Corresponding Codes Where ten digits are shown, they are the ten low-order bits of a 10 to 16-bit word (Word size depends on the system impiementation.) Where four digits are shown, they represent the hexadecimal notation for an entire word (10 to 16 bits). bb Two bits indicating one of the first three general purpose registers: 00 = R0 01 = R1 10 = R2 cccc Four bits giving branch condition, as shown in Table 2-3. ddd Three bits indicating a destination register, RD: 000 = R0 001 = R1 010 = R2 011 = R3 100 = R4 101 = R5 110 = R6 111 = R7 eeee Four bits giving the external branch condition, E. Control signals EBCA0-EBCA3 reflect the state of these four bits. llll One word of immediate data (10 or 16 bits) OBJECT CODE MNEMONIC BRANCH CONDITION DESIGNATION C C = 1 0001 LGT Carry (Logical greater than) NC C = 0 1001 LLT No Carry (Logical less than) OV O = 1 0010 Overflow NOV O = 0 1010 No Overflow PL S = 0 0011 Plus MI S = 1 1011 Minus ZE Z = 1 0100 EQ Zero (equal) NZE Z = 0 1100 NEQ Nonzero (not equal) LT S V O = 1 0101 Less than GE S V O = 0 1101 Greater than or equal LE Z V ( S V O ) = 1 0110 Less that or equal GT Z V (S V O ) = 0 1110 Greater than USC C V S = 1 0111 Unequal sign and carry ESC C V S = 0 1111 Equal sign and carry
Page 1 and 2: Chapter 2 THE GENERAL INSTRUMENT CP
Page 3 and 4: CP1600 PROGRAMMABLE REGISTERS The C
Page 5 and 6: If Registers R4 or R5 provides the
Page 7 and 8: Figure 2-2 CP1600 CPU Signals and P
Page 9 and 10: Figure 2-3. CP1600 Machine Cycles a
Page 11 and 12: Figure 2-6 CP1600 Timing for Memory
Page 13 and 14: The PCIT signal as an input inhibit
Page 15 and 16: THE CP1600 INTERRUPT LOGIC Figure 2
Page 17 and 18: SW The Status Word, whose bits corr
Page 19 and 20: TYPE IMMEDIATE IMMEDIATE OPERATE JU
Page 21: TYPE REGISTER OPERATE (CONTINUED) M
Page 25 and 26: OBJECT MACHINE INSTRUCTION CODE WOR
Page 27 and 28: SUPPORT DEVICES THAT MAY BE USED WI

Chapter 2 THE GENERAL INSTRUMENT CP1600 - Intellivision Brasil

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