Chapter 2 THE GENERAL INSTRUMENT CP1600 - Intellivision Brasil

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Jump instructions use direct memory addressing. Jump instructions are all three words long. The direct address is computed from the second and third memory words as follows: AAAAAABBBBBBBBBB Jump address (binary) YY are enable/disable bits for interrupts XX identity the register where the return address will be stored for JSR XX and YY are described in detail in Table 2-4. You can enable or disable interrupts whenever you execute a Jump or Jump-to-Subroutine instruction. The only difference between a Jump instruction and a Jump-to-Subroutine instruction is that the Jump-to- Subroutin instruction saves the Program Counter contents in Register 4, 5, or 6. The two high-order bits (XX) or the second Jump-to-Subroutine obect code word specifies which of the three registers will be used to hold the return address. Jump-to-Subroutine instructions, like the Jump instruction, allow direct memory addressing only. CP1600 STATUS AND CONTROL FLAGS The CP1600 CPU has four of the standard status flags; in addition, it has some unusual control signals. These are the four standard status flags: Sign (S). This status is set equal to the high-order bit of any arithmetic operation result. Zero (Z). This status is set to 1 when any instruction’s execution creates a zero result. The status is set to 0 for a nonzero result. The Carry (C) and Overflow (O) statuses are standard carry and overflow, as described in Volume 1. Four control signals (EBCA0 - EVCA3) are output during a Branch-on-External (BEXT) instruction. These four signals are output to reflect the low-order four bits of the BEXT instruction’s object code. External logic receives these four signals and (depending on their state), may or may not return a high input via EBCI. If EBCI is returned high, then the BEXT instruction will perform a branch; if EBCI is returned low, then the BEXT instruction will cause the next sequential instruction to be executed. The four control signals EBCA0 - EBCA3 therefore provide the CP1600 with a means of testing 16 external conditions. CP1600 CPU PINS AND SIGNALS 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 1 0 0 X X A A A A A A Y Y B B B B B B B B B B CP1600 CPU pins and signals are illustrated in Figure 2-2. JR or JSR D0 - D15 is a multiplexed Address and Data Bus. Given a total of 40 pins in a package, CP1600 designers have been forced to share 16 pins between addresses and data. Three control signals BDIR, BC1, and BC2, identify the traffic on the Address/Data Bus. External logic (one MSI chip) must decode these three signals to create eight control signals, as summarized in Table 2-1. Remaining signals may be divided into four groups: timing, status/control, interrupt, and DMA. Two timing clock signals are required: F1 and F2. These are complementary clock signals which may be illustrated as follows: F1 F2 Word 2 Word 3
Figure 2-2 CP1600 CPU Signals and Pin Assignments MSYNC is a somewhat unusual signal, as compared to other microcomputer clock signals in this book. Following powerup. MSYNC must be held low for at least 10 milliseconds. On the subsequent rising edge of MSYNC, logic internal to the CP1600 CPU will synchronize the F1 and F2 clock signals to start a new machine cycle. Most of the CPU devices we have described in this book use a reset signal or have internal powerup logic which performs this clock synchronization. Now consider the status and control signals. First of all, there are the four control outputs which we have already described: EBCA0 - EBCA3. There is one conditional Branch instruction (BEXT) which will only branch if a high signal is input via EBCI. When the BEXT instruction is executed, the low-order four BEXT instruction object code bits are output via EBCA0 - EBCA3. External logic is supposed to decode these four signals by whatever means are appropriate — and thence determine whether EBCI shouId be input high or low. A high input, as we have just stated, will result in a branch; a low input wiII cause the next sequential instruction to be executed. In reality, there is no connection within CP1600 CPU logic between the EBCI input and the four EBCA0-EBCA3 outputs. So far as external logic is concerned, the execution of a BEXT instruction is identified by signal levels output and maintained on the EBCA0 - EBCA3 outputs. While the EBCI input determines whether a branch will or will not occur. How external logic chooses to determine whether EBCI will be set high or low is entirely up to external logic. The only vital function served by EBCA0 - EBCA3 is to identify the instant at which a BEXT instruction is executed. Another unusual control signal provided by the CP1600 is PCIT: this is a bidirectional signal. When input low, this signal prevents the Program Counter from being incremented following an instruction fetch. This signal is also output as a low pulse following execution of a software interrupt instruction. Instruction timing separates the active input and
Page 1 and 2: Chapter 2 THE GENERAL INSTRUMENT CP
Page 3 and 4: CP1600 PROGRAMMABLE REGISTERS The C
Page 5: If Registers R4 or R5 provides the
Page 9 and 10: Figure 2-3. CP1600 Machine Cycles a
Page 11 and 12: Figure 2-6 CP1600 Timing for Memory
Page 13 and 14: The PCIT signal as an input inhibit
Page 15 and 16: THE CP1600 INTERRUPT LOGIC Figure 2
Page 17 and 18: SW The Status Word, whose bits corr
Page 19 and 20: TYPE IMMEDIATE IMMEDIATE OPERATE JU
Page 21 and 22: TYPE REGISTER OPERATE (CONTINUED) M
Page 23 and 24: The following notation is used in T
Page 25 and 26: OBJECT MACHINE INSTRUCTION CODE WOR
Page 27 and 28: SUPPORT DEVICES THAT MAY BE USED WI

Chapter 2 THE GENERAL INSTRUMENT CP1600 - Intellivision Brasil

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