Uboot中start.S源码的指令级的详尽解析

instructions that access CP15. Using other values results in unpredictable
behavior”
CP15有很多个寄存器,分别叫做寄存器0(Register 0),到寄存器15(Register 15),
每个寄存器分别控制不同的功能,而且有的是只读,有的是只写,有的是可读写。
而且这些寄存器的含义,随着版本ARM内核版本变化而不断扩展,详情请参考这个网址:
http://www.heyrick.co.uk/assembler/coprocmnd.html
其中,根据我们此处关心的内容,摘录部分内容如下:
“ARM 710
Register 7 - IDC flush (write only)
。。。。。。
Any data written to this location will cause the IDC
(Instruction/Data cache) to be flushed.
StrongARM SA110
。。。
Register 7 - Cache control (write only)
Any data written to this location will cause the selected cache to
be flushed.
The OPC_2 and CRm co-processor fields select which cache
operation should occur:
o Function OPC_2 CRm Data
o Flush I + D %0000 %0111 -
o Flush I %0000 %0101 -
o Flush D %0000 %0110 -
o Flush D single %0001 %0110 Virtual address
o Clean D entry %0001 %1010 Virtual address
o Drain write buf. %0100 %1010 -
Register 8 - TLB operations (write only)
Any data written to this location will cause the selected TLB flush
operation.
The OPC_2 and CRm co-processor fields select which cache
operation should occur:
o Function OPC_2 CRm Data
o Flush I + D %0000 %0111 -
o Flush I %0000 %0101 -
o Flush D %0000 %0110 -
o Flush D single %0001 %0110 Virtual address”
而MCR的详细的语法为:
“MCR指令
MCR指令将ARM处理器的寄存器中的数据传送到协处理器寄存器中。如果协处理器不能成功地执