ECE 401L COMMUNICATIONS LABORATORY LAB 7 - University of ...

ECE 401L COMMUNICATIONS LABORATORY
LAB 7: Noncoherent Detection of Frequency-Shift Keying (FSK)
1. Objective
In this final laboratory exercise, students will design, construct and test a circuit for noncoherent
detection of frequency-shift keying (FSK) using the V.21 modem standard.
2. Background
The circuit you are to design should demodulate an FSK signal in what is referred to by the
International Telecommunications Union (I.T.U.) as the V.21 modem standard. The V.21 format
communicates 1's and 0's by sending either a 1650 Hz tone or an 1850 Hz tone, respectively, for
1/300-th of a second. Thus the overall data rate is 300 bits/second (one bit is sent in 1/300-th of a
second). Even though 300 bps is quite slow compared with the theoretical maximum of 56
kilobits per second over a phone line, the V.21 format is still used in almost every modem call.
This is due to the fact that receiving and decoding it is relatively simple. A V.21 modem call can
be received without using complex techniques such as channel equalization or matched filters.
Furthermore, it can be received accurately even in the presence of a significant amount of noise.
For these reasons, V.21 is used as an initial handshake between two modems, meaning that V.21
is a way to communicate some basic startup/control information between the two modems. You
can hear the V.21 modem tones when a V.34, V.90, or V.92 phone line modem or fax machine
starts a phone call. The V.21 format is also used to transmit caller ID information over the phone
line.
It is recommended that your design be based on the nocoherent FSK system shown in
Fig. 1 (top). It includes two bandpass filters (one centered at 1650 Hz and one centered at 1850
Hz). While simple passive RLC bandpass filters can work, there are some practical problems
associated with generating the small bandwidth required (e.g., a large L is required to get the
narrow bandwidth for a series RLC). To avoid such problems, use the high-Q active BPF shown
in the appendix (Fig. 15.26). The design equations are also provided. You can follow Example
15.12 and use Q=10 and K=2 (however, the system will work with a lower Q). You want
accurate center frequencies so match your resistance values carefully. You may wish to make R3
variable (or partially variable) to allow you to tune your center frequency (while this may change
Q slightly, matching the center frequency is more important than getting a specific Q value).
Each BPF is followed by an envelope detector. A time constant of approximately 3 ms is
recommended for the envelope detectors, but you may need to experiment to get the best results.
Finally the outputs of the two envelope detectors go to a comparator, which makes the decision
regarding the transmitted symbol (0 or 1). At the transitions, many frequency components are
present and the decision may appear erratic. Thus, in practice one would sample the inputs to the
comparator (or the output of the comparator) in the middle of each received symbol (timing
information is needed in this case). Here we will not concern ourselves with the sampling of the
output. Rather we will observe the output of the comparator at all times. The comparator is
simply constructed by applying the output of one envelope detector to the + terminal of an openloop
op-amp and the other envelope detector output to the - terminal. The output will shoot to
the positive supply voltage if the positive input terminal is higher in voltage than the negative
terminal. Likewise, the output will shoot to the negative supply voltage when the reverse is true.
These output voltages will represent our decoded binary signal (further signal conditioning could
be applied to convert these output voltages to TTL voltage levels, for example).
R. C. Hardie, Department of Electrical and Computer Engineering,
University of Dayton, Fall 2003
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Figure 1: (top) Noncoherent demodulation of FSK (bottom) coherent demodulation of FSK.
2. Prelab Assignment
You should create a preliminary design for your FSK demodulator. Refinements to the design
may be required as you construct and test your circuit. The design can be done as a lab group or
individually. Prepare and submit a clear schematic for your design (at least one per lab group).
Specify the key design equations used for each module in the design (i.e., BPF center frequency,
BPF bandwidth, BPF Q-factor, time constant of envelope detectors, etc).
3. Procedure
3.1 BPF
It is recommended that you construct your circuit in modules and test each module. In particular,
construct each BPF and test the frequency response. Make sure the center frequency of each is
very close to the desired frequency (note the two center frequencies are only 200 Hz apart). You
may need to adjust your resistor values (possibly with a potentiometer for R3 to tune the BPF
center frequencies). Once you are satisfied with the frequency response you observe, collect at
least 10 magnitude frequency response measurements (output peak-to-peak voltage divided by
input peak-to-peak voltage) around the center frequency of each BPF and generate a magnitude
frequency response plot for each BPF. Do the BPFs behave as expected? It will be helpful to
show the two frequency-response plots on the same axis in your report, since they work as a pair.
Generate an FSK signal with the waveform generator. Be sure to correctly enter the two
frequencies. Set the FSK rate (1/2 the bit rate) initially to 10 Hz to make it easier to test and
debug your circuit. Inspect the output of one BPF on Channel 1 and the output of the other on
Channel 2. One BPF output should have a large amplitude, while the other is small, and vice
versa. If the BPFs appear to be working correctly, increase the FSK rate to 150 Hz (300 bits per
second). Capture the outputs of the two BPFs simultaneously at this V.21 rate for your report.
R. C. Hardie, Department of Electrical and Computer Engineering,
University of Dayton, Fall 2003
2

3.2 Envelope Detectors
Next, construct the envelope detectors and test them. Keep in mind they must allow the signal to
transition every 1/300-th of a second, but maintain a relatively constant output voltage during the
duration of a bit (smoothing out the 1650 Hz or 1850 Hz signal coming in). We recommend
starting with a time constant of approximately 3 ms (but again, you may need to tune it for
optimum performance). Construct the envelope detectors and connect them to the outputs of the
BPFs. Reduce the FSK rate back to 10 Hz signal with the waveform generator and inspect the
output of one BPF on Channel 1 and the output of the corresponding envelope detector on
Channel 2. The output of the envelope detector should look like a square wave and track the
envelope of the BPF output (although some ripple may still be visible). Be sure your input
voltage is sufficiently high for the envelope detector to operate correctly. Now increase the FSK
rate to 150 Hz. Once you are satisfied with the envelope detectors, capture both envelope
detector outputs simultaneously with an FSK rate of 150Hz for the report.
3.3 Comparator
Lastly, construct and test the comparator. Apply any periodic input to the comparator and look
for the square-wave output that should result (remember the op-amp has no feedback path). Now
connected the comparator to the rest of the circuit and try it! Start by using an FSK rate of 10Hz.
Verify the output (it should be a square wave synced with the FSK signal). Increase your FSK
rate to 150 Hz and capture the output. Demonstrate the operation of the complete circuit to the
TA.
3.4 The “Bit-rate Challenge” and Improvements (Optional)
If time permits try to see how high a bit rate you can demodulate while maintaining a “clean”
output (i.e., it stays high for one bit duration and stays low for the next with little or no
oscillations over the duration of a bit). One thing that may improve the system’s performance is
to add an RC LPF at the output of the comparator to remove any unwanted oscillations. Use a
cutoff frequency above 2x the bit rate in Hertz (to pass the bit pulses) and below 1650 Hz (to
suppress the oscillations, tune for optimum performance). Now, pass the output of the LPF
through another comparator that compares with zero (ground the negative terminal). Does this
output look cleaner? Let’s have a friendly competition to see who can get a clean output at the
highest bit rate (the “bit-rate” challenge!).
3.5 Audible Test
Now let’s try to construct an “air” modem. Since the V.21 is designed for audible channels
(phone lines), we can broadcast the FSK signal audibly and detect it with a microphone. Reduce
the amplitude of the FSK signal and then connect a speaker to the waveform generator.
Construct an amplifier with a gain of approximately 100 and connect a microphone to the input of
the amplifier and connect the output of the amplifier to the FSK demodulator circuit. Slowly
increase the amplitude of the FSK signal using the waveform generator and place the microphone
near the speaker. Now display the FSK signal on Channel 1 and the output of your FSK
demodulator circuit on Channel 2. Does it work? If necessary, reduce the FSK rate. Capture an
output waveform.
R. C. Hardie, Department of Electrical and Computer Engineering,
University of Dayton, Fall 2003
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3. Lab Write-up
This lab write-up should be done in a formal report fashion. It should be done in Word and be
formatted according to the guidelines provided on the ECE401L website (under “formal report
guidelines”). Provide information regarding the objective of the lab, show all theoretical design
equations and calculations (use the equation editor), include sufficient experimental results to
demonstrate the efficacy of your design, and provide meaningful conclusions and
recommendations to possibly improve the design.
Bonus: Provide us with an interesting scientific question and answer that we can use for future
bonus questions (in the spirit of the previous bonus questions).
APPENDIX: HIGH-Q ACTIVE BPF
R. C. Hardie, Department of Electrical and Computer Engineering,
University of Dayton, Fall 2003
4

R. C. Hardie, Department of Electrical and Computer Engineering,
University of Dayton, Fall 2003
5

R. C. Hardie, Department of Electrical and Computer Engineering,
University of Dayton, Fall 2003
6

R. C. Hardie, Department of Electrical and Computer Engineering,
University of Dayton, Fall 2003
7

R. C. Hardie, Department of Electrical and Computer Engineering,
University of Dayton, Fall 2003
8