Design of De-Emphasis and Equalization Circuits for Gigabit Serial ...

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Control Waveforms � Timing Diagram to show signals that used by the Edge Detection Circuit � Output of XOR gate is high after every transition
Transmitter Top Level Implementation � Adjustable De-emphasis through Vcontrol1,2,3 (digital control) � Four levels of De-emphasis possible 6.5dB, 3.5dB, 1.75 dB and 0dB � All Circuits realized using UMC’s 0.13um CMOS process � Circuits designed using Ansoft DesignerRF and Nexxim vee i400u5 i400u6 i800u3 i400u5 i400u6 i400u7 i800u4 i800u3 Vss Vdd U3 CurrentSource8 Vdd DIS vee vee ckl spinh spinl Vdd Vdd U54 Driver5 vee i400u4 i400u2 i20m i800u1 i800u1 i400u1 i400u1 i400u2 i400u2 i400u3 i400u3 vee i400u4 i400u4 i800u1 i800u1 i800u2 i800u2 Vdd ckh dl dh dh dl ckh ckl Vss vee Vdd i400u1 i400u2 inh U31 DFlipflop4 i400u1 i400u2 qh ql Vdd i20m inl outl Vss Output Driver D Flip-flop XOR Gate outh ah al bh bl i400u3 i400u XORgate6 Vss vee outh Vdd Vdd U6 outh outl outl inh inl inh inl i400u5 i400u2 i800u2 i800u1 inh inl i400u6 i400u2 i800u3 i800u1 Vdd U21 Demphcurrsrc4 Vdd Vss Vdd Vss vee Vdd Vss vee Adjustable Current Source Idemph DIS U65 Demphcurrsrc4 Idemph DIS U75 Demphcurrsrc4 Idemph DIS VCONTROL1 VCONTROL2 VCONTROL3 User Programmed De-emphasis (0dB, 1.8dB, 3.5dB,6.2dB)
Page 1 and 2: Design of De-Emphasis and Equalizat
Page 3 and 4: Why High Speed Serial Interconnects
Page 5 and 6: FR4 loss •Channel loss performs l
Page 7 and 8: Transmit vs. Receive Equalization
Page 9: De-Emphasis Architecture Use edge d
Page 13 and 14: dl dh ckh ckl Vss Flip Flop � D F
Page 15 and 16: XOR Gate � Gilbert Cell Variation
Page 17 and 18: Receiver Input Stage � CML input
Page 19 and 20: Output with De-emphasis � Every t
Page 21 and 22: Vss Package inh M1558 M1559 inl P_1
Page 23 and 24: De-emphasis at work! � Xilinx Vir
Page 25 and 26: Receive Equalization � Passive Ne
Page 27 and 28: Combination of De-emphasis and Rece

Design of De-Emphasis and Equalization Circuits for Gigabit Serial ...

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