Design of De-Emphasis and Equalization Circuits for Gigabit Serial ...

More documents

Recommendations

Info

Vss Vdd m=30 w=1u l=10u ql D Latch � Current Steering D latch with positive feedback Data Vdd Vdd dh n_bpw_12_rf n_bpw_12_rf dl Clock lf=0.12u wf=1u nf=4 M=1 wt=4u qh Vdd Vdd ckh n_bpw_12_rf n_bpw_12_rf ckl Vss Vdd i400u n_bpw_12_rf r_zbt_m=0.336k rnhr_rf Vdd Vdd Vss Vss lf=0.12u wf=1u nf=4 M=1 wt=4u Vss Vss lf=0.12u wf=1u nf=4 M=4 wt=4u Vss m=30 w=1u l=10u r_zbt_m=0.336k rnhr_rf lf=0.12u wf=1u nf=4 M=1 wt=4u n_bpw_12_rf lf=0.12u wf=1u nf=4 M=4 wt=4u Vdd Vss n_bpw_12_rf lf=0.12u wf=1u nf=4 M=4 wt=4u Vdd Vss Vss Vss Vdd lf=0.12u wf=1u nf=4 M=4 wt=4u n_bpw_12_rf lf=0.12u wf=1u nf=4 M=4 wt=4u
XOR Gate � Gilbert Cell Variation bh ah al Vdd outh outl i400u Vss bl l=10u w=1u m=24 rnhr_rf r_zbt_m=0.42k l=10u w=1u m=24 rnhr_rf r_zbt_m=0.42k n_bpw_12_rf nf=4 lf=0.12u wf=1u M=2 wt=4u n_bpw_12_rf nf=4 lf=0.12u wf=1u M=2 wt=4u n_bpw_12_rf nf=4 lf=0.12u wf=1u M=2 wt=4u n_bpw_12_rf nf=4 lf=0.12u wf=1u M=2 wt=4u n_bpw_12_rf nf=4 lf=0.12u wf=1u M=2 wt=4u n_bpw_12_rf nf=4 lf=0.12u wf=1u M=2 wt=4u n_bpw_12_rf nf=4 lf=0.12u wf=1u M=4 wt=4u n_bpw_12_rf nf=4 lf=0.12u wf=1u M=1 wt=4u n_bpw_12_rf nf=4 lf=0.12u wf=1u M=1 wt=4u n_bpw_12_rf nf=4 lf=0.12u wf=1u M=1 wt=4u n_bpw_12_rf nf=4 lf=0.12u wf=1u M=1 wt=4u n_bpw_12_rf nf=4 lf=0.12u wf=1u M=1 wt=4u Vdd Vdd Vdd Vdd Vdd Vdd Vdd Vdd Vdd Vdd Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vdd Vss Vdd Vss Vdd Vss Vdd Vss A B
Page 1 and 2: Design of De-Emphasis and Equalizat
Page 3 and 4: Why High Speed Serial Interconnects
Page 5 and 6: FR4 loss •Channel loss performs l
Page 7 and 8: Transmit vs. Receive Equalization
Page 9 and 10: De-Emphasis Architecture Use edge d
Page 11 and 12: Transmitter Top Level Implementatio
Page 13: dl dh ckh ckl Vss Flip Flop � D F
Page 17 and 18: Receiver Input Stage � CML input
Page 19 and 20: Output with De-emphasis � Every t
Page 21 and 22: Vss Package inh M1558 M1559 inl P_1
Page 23 and 24: De-emphasis at work! � Xilinx Vir
Page 25 and 26: Receive Equalization � Passive Ne
Page 27 and 28: Combination of De-emphasis and Rece

Design of De-Emphasis and Equalization Circuits for Gigabit Serial ...

Create successful ePaper yourself

Delete template?

Save as template?