Complementary Folded Cascode OpAmps for Low Voltage ...
Complementary Folded Cascode OpAmps for Low Voltage ...
Complementary Folded Cascode OpAmps for Low Voltage ...
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IC<br />
OvG<br />
<strong>Complementary</strong> <strong>Folded</strong> <strong>Cascode</strong><br />
<strong>OpAmps</strong> <strong>for</strong> <strong>Low</strong> <strong>Voltage</strong> Applications<br />
U. Kleine and F. Roewer<br />
Otto von Guericke University<br />
Magdeburg
IC<br />
OvG<br />
Motivation<br />
Introduction<br />
Example MOS <strong>Folded</strong>-<strong>Cascode</strong><br />
<strong>Folded</strong> <strong>Cascode</strong> OpAmp<br />
- Output Swing<br />
- Poles and Zeros<br />
<strong>Complementary</strong> <strong>Folded</strong>-<strong>Cascode</strong><br />
<strong>Folded</strong> <strong>Cascode</strong> <strong>OpAmps</strong><br />
- 3 Novel Structures<br />
- Measurement Results<br />
Conclusion
IC<br />
OvG<br />
One Stage<br />
OpAmp<br />
Unity gain frequency<br />
DC-Gain DC<br />
Motivation<br />
gm<br />
f 0 =<br />
2 C<br />
Gain A 0 = gm r01<br />
1
IC<br />
OvG<br />
Output Resistance<br />
MOS <strong>Folded</strong>-<strong>Cascode</strong> OpAmp<br />
Vout = Vdd – |VTp VTp|<br />
- 2 Vov<br />
Vout = -Vss Vss<br />
+ 2 Vov<br />
Output Resistance R out = { (ro2<br />
|| ro12<br />
) + ro2A<br />
[ 1+<br />
( g m2A + g mb2A )( ro2<br />
|| ro12<br />
) ] } || { ro4<br />
+ ro4A<br />
[ 1+<br />
( g m4A + g mb4A )( ro4<br />
) ] }
IC<br />
OvG<br />
A<br />
0<br />
= g<br />
= g<br />
= g<br />
DC-Gain DC Gain<br />
m2<br />
m2<br />
m2<br />
ω<br />
= C<br />
1<br />
R<br />
out<br />
Poles and Zeros<br />
{ (ro2<br />
|| ro12<br />
) + ro2A<br />
[ 1+<br />
( g m2A + g mb2A )( ro2<br />
|| ro12<br />
) ] } || { ro4<br />
+ ro4A<br />
[ 1+<br />
( g m4A + g mb4A )( ro4<br />
) ] }<br />
{ r ( g + g )( r || r ) } || { r ( g + g )( r ) }<br />
o2A<br />
m2A<br />
First Pole<br />
1<br />
≈ C<br />
1<br />
R<br />
out<br />
mb2A<br />
o2<br />
o12<br />
o4A<br />
m4A<br />
mb4A<br />
{ r ( g + g )( r || r ) } || { r ( g + g )( r ) }<br />
o2A<br />
m2A<br />
mb2A<br />
o2<br />
o12<br />
o4A<br />
m4A<br />
mb4A<br />
o4<br />
o4
IC<br />
OvG<br />
U -<br />
I<br />
B1<br />
U<br />
Common Mode <strong>Voltage</strong> Range<br />
(J.H. Huijsing und D. Linebarger)<br />
UDD<br />
U<br />
a<br />
R R<br />
U<br />
SGp<br />
1 2<br />
dsat<br />
U<br />
+<br />
U<br />
U<br />
U<br />
dsat<br />
SGp<br />
CM<br />
U<br />
U<br />
U<br />
CM<br />
GSn<br />
dsat<br />
U<br />
U<br />
R R<br />
3 4<br />
U<br />
U - U +<br />
dsat<br />
GSn<br />
a<br />
USS<br />
I<br />
B2<br />
U<br />
U<br />
DD<br />
SS
IC<br />
OvG<br />
Rail-to-Rail-Difference Stage
IC<br />
OvG<br />
First Novel Structure with Rail-to-Rail Input Stage
IC<br />
OvG<br />
Small Signal Quantities of the First Amplifier<br />
Asymmetric Current Mirrors<br />
I<br />
I<br />
D, M7<br />
D, M8<br />
DC Gain<br />
i<br />
out, a<br />
=<br />
v<br />
WM6<br />
WM6<br />
I bias I bias I bias WM6<br />
= I D, M6 − I D, M4 = I D, M3/5 − I D, M4 = ⋅ − = ⋅ −1<br />
W<br />
W 2 2 2 W<br />
M5<br />
WM9<br />
WM9<br />
I bias I bias I bias WM9<br />
= I D, M9 − I D, M2 = I D, M1/10 − I D, M2 = ⋅ − = ⋅ −1<br />
W<br />
W 2 2 2 W<br />
diff<br />
2<br />
⋅<br />
© ©<br />
<br />
g<br />
m, M1/M2<br />
⋅<br />
<br />
<br />
A<br />
M10<br />
V0<br />
1+<br />
g<br />
=<br />
m, M10<br />
v<br />
v<br />
out<br />
diff<br />
g<br />
+ g<br />
=<br />
i<br />
m, M9<br />
out<br />
ds, M10<br />
v<br />
⋅ r<br />
diff<br />
+ g<br />
out<br />
ds, M1<br />
M5<br />
M10<br />
<br />
<br />
+ g<br />
m, M3/M4<br />
⋅<br />
<br />
<br />
1+<br />
g<br />
£ ¤ £<br />
m, M5<br />
¥<br />
£ ¤ £<br />
¥<br />
M5<br />
g<br />
+ g<br />
M10<br />
m, M6<br />
ds, M5<br />
+ g<br />
¢<br />
¡<br />
¢<br />
¡<br />
ds, M3<br />
<br />
¦ § ¦<br />
<br />
¨
IC<br />
OvG<br />
Small Signal Quantities of the First Amplifier (2)<br />
Simplified DC Gain<br />
A<br />
V0, a<br />
1<br />
2<br />
1+<br />
Poles and Zeros<br />
A<br />
V, a<br />
=<br />
⋅<br />
(p) =<br />
C<br />
P =<br />
g<br />
<br />
1<br />
2<br />
<br />
⋅<br />
<br />
2<br />
m7<br />
W<br />
W<br />
<br />
1+<br />
⋅ C<br />
⋅ g<br />
M6<br />
M5<br />
4<br />
W<br />
W<br />
m8<br />
⋅<br />
(g<br />
<br />
⋅ p<br />
<br />
M6<br />
M5<br />
2<br />
ds, M6<br />
g<br />
C<br />
+<br />
+ g<br />
m, M7<br />
⋅<br />
P ⋅ C<br />
§ ¨ §<br />
©<br />
2<br />
l<br />
⋅ g<br />
g<br />
<br />
¤¢¥<br />
ds, M4<br />
+ g<br />
g<br />
g<br />
) ⋅ g<br />
mb, M7<br />
p ⋅ C<br />
(g<br />
⋅ p +<br />
m7<br />
¦<br />
m7<br />
<br />
+ C<br />
⋅ g<br />
m8<br />
m, M1/M2<br />
2<br />
4<br />
m8<br />
ds, M7<br />
+ 1<br />
ds, M6<br />
⋅ g<br />
+ g<br />
m8<br />
©<br />
+ g<br />
g<br />
+<br />
⋅ g<br />
§ ¨ §<br />
g<br />
ds, M4<br />
m7<br />
m, M3/M4<br />
ds, M8<br />
⋅ p + 1<br />
g<br />
m, M1/M2<br />
) ⋅ g<br />
⋅ ( g<br />
m, M8<br />
+<br />
<br />
ds, M7<br />
ds, M9<br />
+ g<br />
p ⋅ C<br />
<br />
g<br />
m7<br />
+ g<br />
mb, M8<br />
4<br />
g<br />
+<br />
ds, M2<br />
+ 1<br />
ds, M8<br />
©<br />
)<br />
⋅ g<br />
§ ¨ §<br />
⋅ ( g<br />
m, M3/M4<br />
ds, M9<br />
g<br />
m8<br />
+ g<br />
£<br />
¢¡<br />
ds, M2<br />
)
IC<br />
OvG<br />
Second New Amplifier
IC<br />
OvG<br />
Small Signal Quantities<br />
Proper Operation Point with 0 < ID,M21 ID,M21<br />
= ID,M22 ID,M22<br />
< 0.5 IBIAS<br />
A<br />
V0, b<br />
V, b<br />
=<br />
g<br />
ds, M7<br />
⋅ ( g<br />
l<br />
ds, M6<br />
g<br />
m, M7<br />
Poles and Zeros<br />
A<br />
(p) =<br />
g<br />
P ⋅ C ⋅ p +<br />
P =<br />
i out, b ≈ v diff ⋅ ( g m, M1/M2 + g m, M3/M4 )<br />
+ g<br />
+ g<br />
ds, M7<br />
g<br />
ds, M4<br />
<br />
C<br />
mb, M7<br />
p ⋅ C<br />
g m8<br />
⋅ (g<br />
2<br />
m7<br />
<br />
⋅ C<br />
⋅ g<br />
g<br />
+ g<br />
2<br />
ds, M6<br />
4<br />
m8<br />
m, M1/M2<br />
ds, M21<br />
+ 1<br />
+ g<br />
g<br />
⋅ p<br />
m7<br />
2<br />
©<br />
+ g<br />
) g<br />
+<br />
⋅ g<br />
§ ¨ §<br />
ds, M4<br />
C<br />
+<br />
m, M3/M4<br />
ds, M8<br />
m, M1/M2<br />
2<br />
+ g<br />
⋅ g<br />
g<br />
+<br />
⋅ ( g<br />
<br />
ds, M21<br />
m7<br />
m7<br />
+ C<br />
⋅ g<br />
ds, M9<br />
g<br />
m, M8<br />
+ g<br />
+ g<br />
ds, M2<br />
mb, M8<br />
p ⋅ C 4<br />
+ 1 ⋅ g<br />
g m7<br />
) g ds, M8 ⋅ ( g<br />
+<br />
<br />
4<br />
m8<br />
⋅ g<br />
m8<br />
©<br />
§ ¨ §<br />
⋅ p + 1<br />
+ g<br />
m, M3/M4<br />
ds, M9<br />
ds, M22<br />
+ g<br />
g<br />
m8<br />
)<br />
ds, M2<br />
+ g<br />
ds, M22<br />
)
IC<br />
OvG<br />
Third New Amplifier
IC<br />
OvG<br />
Proper Operation Point Current<br />
i<br />
out, c<br />
Poles and Zeros<br />
A<br />
=<br />
V, c<br />
v<br />
diff<br />
2<br />
Small Signal Quantities<br />
⋅<br />
¤ ¤ ¤ ¤ ¥ ¤<br />
¦<br />
g<br />
m, M1/M2<br />
+ g<br />
l<br />
⋅<br />
m, M3/M4<br />
<br />
m8<br />
⋅<br />
p ⋅ C<br />
g<br />
(p) =<br />
g<br />
P ⋅ C ⋅ p +<br />
P =<br />
g<br />
C<br />
2<br />
m7<br />
£ ¤ £<br />
¥<br />
⋅ C<br />
⋅ g<br />
4<br />
m8<br />
<br />
1+<br />
g<br />
2<br />
<br />
ds, M7<br />
⋅ p<br />
<br />
1+<br />
g<br />
+ 1<br />
2<br />
m, M10<br />
⋅ (g<br />
m, M5<br />
⋅ g<br />
ds, M6<br />
g<br />
C<br />
+<br />
¢<br />
¡<br />
2<br />
m7<br />
+ g<br />
+ g<br />
m, M1/M2<br />
⋅ g<br />
g<br />
ds, M10<br />
+ g<br />
g<br />
m7<br />
m7<br />
ds, M5<br />
+<br />
m, M9<br />
g<br />
£ ¤ £<br />
ds, M4<br />
+ C<br />
⋅ g<br />
+ g<br />
m8<br />
m, M6<br />
+ g<br />
ds, M1<br />
ds, M3<br />
+ g<br />
+ g<br />
ds, M21<br />
ds, M22<br />
p ⋅ C 4<br />
+ 1 ⋅ g<br />
g m7<br />
) g ds, M8 ⋅ ( g<br />
+<br />
g<br />
4<br />
¥<br />
⋅ g<br />
m8<br />
⋅ p + 1<br />
¢<br />
¡<br />
m8<br />
§ ¨ §<br />
ds, M9<br />
©<br />
§ ¨ §<br />
m, M3/M4<br />
©<br />
£<br />
¡<br />
+ g<br />
ds, M2<br />
)
IC<br />
OvG<br />
First Pole<br />
Gain Bandwidth<br />
Product<br />
Gain Bandwidth Product<br />
GBW<br />
f<br />
=<br />
1<br />
=<br />
A<br />
2<br />
V0<br />
1<br />
⋅ r<br />
⋅ f<br />
1<br />
out<br />
≈<br />
⋅ C<br />
g<br />
L<br />
m, M1/M2<br />
2<br />
+ g<br />
⋅ C<br />
m, M3/M4<br />
L
IC<br />
OvG<br />
Chip Microphotograph of the Third <strong>Folded</strong>-<strong>Cascode</strong><br />
Amplifier
IC<br />
OvG<br />
Chip Microphotograph of the First <strong>Folded</strong>-<strong>Cascode</strong><br />
Amplifier
IC<br />
OvG<br />
Chip Microphotograph of the Second <strong>Folded</strong>-<br />
<strong>Cascode</strong> Amplifier
IC<br />
OvG<br />
Gain (dB)<br />
90<br />
80<br />
70<br />
60<br />
50<br />
40<br />
30<br />
20<br />
10<br />
0<br />
-10<br />
-20<br />
-30<br />
Frequency Response of the <strong>OpAmps</strong><br />
1,E+02 1,E+03 1,E+04 1,E+05 1,E+06 1,E+07 1,E+08<br />
Frequency (Hz)<br />
0<br />
-15<br />
-30<br />
-45<br />
-60<br />
-75<br />
-90<br />
-105<br />
-120<br />
-135<br />
-150<br />
-165<br />
-180<br />
Phase (°)<br />
Gain a (dB)<br />
Gain b (db)<br />
Gain c (db)<br />
Phase a (°)<br />
Phase b (°)<br />
Phase c (°)
IC<br />
OvG<br />
Gain (dB)<br />
Frequency Response of the OpAmp <strong>for</strong> Different<br />
Bias Current<br />
80<br />
70<br />
60<br />
50<br />
40<br />
30<br />
20<br />
10<br />
0<br />
-10<br />
1,E+02 1,E+03 1,E+04 1,E+05 1,E+06 1,E+07 1,E+08<br />
Frequency (Hz)<br />
0<br />
-20<br />
-40<br />
-60<br />
-80<br />
-100<br />
-120<br />
-140<br />
-160<br />
-180<br />
Phase (°)<br />
Gain@100µA (dB)<br />
Gain@200µA (dB)<br />
Gain@300µA (dB)<br />
Phase@100µA (°)<br />
Phase@200µA (°)<br />
Phase@300µA (°)
IC<br />
OvG<br />
VDD DD = 5V,<br />
C1 = 5pF<br />
Differential<br />
gain AV0<br />
Differential<br />
GBW<br />
Phase Margin<br />
ϕ<br />
Power<br />
dissipation<br />
Input offset<br />
voltage<br />
Slew rate<br />
(rise/fall)<br />
Input noise @<br />
10kHz<br />
CMRR<br />
Ibias bias = 150µA<br />
(V/V)<br />
(MHz)<br />
(°)<br />
(mW)<br />
(mV)<br />
(V/µs)<br />
(nV/√ (nV/ Hz)<br />
(V/V)<br />
Per<strong>for</strong>mance Table<br />
Opamp a)<br />
81,5 dB<br />
20,5<br />
68,5<br />
3,9<br />
-1.5 1.5 .. 5.6<br />
-5,8/6,6 5,8/6,6<br />
18,0<br />
>60dB<br />
Opamp b)<br />
69,5 dB<br />
21,5<br />
77,5<br />
3,8<br />
-4.9 4.9 .. 3.5<br />
-4,9/3.5 4,9/3.5<br />
17,3<br />
>51dB<br />
Opamp c)<br />
70,5 dB<br />
21,8<br />
78,2<br />
4,1<br />
-4.7 4.7 .. 1.8<br />
-4,8/1.8 4,8/1.8<br />
17,0<br />
>51dB
IC<br />
OvG<br />
VDD DD = 5V,<br />
C1 = 5pF<br />
Input voltage<br />
range<br />
Output<br />
voltage range<br />
Size (length *<br />
width)<br />
Ibias bias = 150µA<br />
(V)<br />
(V)<br />
(µm²)<br />
Per<strong>for</strong>mance Table (2)<br />
Opamp a)<br />
0.0 .. 5.0<br />
0.7 .. 4.3<br />
143 * 103<br />
Opamp b)<br />
0.0 .. 5.0<br />
0.6 .. 4.4<br />
149 * 103<br />
Opamp c)<br />
0.0 .. 5.0<br />
0.6 .. 4.4<br />
148 * 103
IC<br />
OvG<br />
Conclusions<br />
➤Three Three Different <strong>Folded</strong>-<strong>Cascode</strong><br />
<strong>Folded</strong> <strong>Cascode</strong> Amplifiers<br />
➤Rail Rail-to to-rail rail input range<br />
➤Power Power supply voltage range: 2.5V-5V 2.5V 5V<br />
➤Bandwidth Bandwidth 100MHz@1pF Load, 20MHz@5pF<br />
➤Compact Compact layout by use of module generator<br />
➤Applications: Applications: SC circuits, DA / AD converter ...<br />
➤Published Published in J. SSC August 2002