Internal Hardware Design of a Microcontroller in VLSI

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The register controller subsystem accepts a 2-bit controller value, which selects which of the four output bits will take the input clock pulse. This is done by using a 2:4 decoder, as shown in Figure 7. Figure 7: Gate-Level Design of the Register Controller Each of the four registers and the accumulator use eight NOR gate, falling-edge triggered D flip-flops as shown in Figure 8. The designers also added another input to the NOR gate that outputs the Q value. This third input was used as the flip-flop’s reset. Figure 8: Gate-Level Design of the NOR Gate D Flip-flop
As shown in Figure 9, the comparator design used XOR gates to compare the register and timer values bit by bit. A NAND gate was used to verify if all eight of the bits were the same. Complete System Figure 9: Gate-Level Design of the Comparator Subsystem The complete system is shown in Figure 10. The designers used macros to create blocks for various subsystems.
Page 1 and 2: Internal Hardware Design of a Micro
Page 3 and 4: Table of Contents Introduction 4 Sy
Page 5 and 6: Block Diagrams Clock Controller Sub
Page 7 and 8: Register Subsystem The 8-bit accumu
Page 9: The clock controller in Figure 6 ha
Page 13 and 14: VLSI Circuit Diagrams in L-Edit The
Page 15 and 16: Figure 13: 16-bit Timer Subsystem i
Page 17 and 18: The VLSI design for the complete su
Page 19 and 20: showing the most significant four b
Page 21 and 22: Complete System: Figure 21: Compara
Page 23 and 24: VHDL Software Design The VHDL code
Page 25 and 26: Appendix: VHDL Subsystem Code and S
Page 27 and 28: Clock Controller Subsystem: library
Page 29 and 30: signal d,q: std_logic_vector (15 do

Internal Hardware Design of a Microcontroller in VLSI

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