Power Management in Embedded Systems - DAIICT Intranet

Power Management in
Embedded Systems
Udayan Kumar
(200101227)
Kundan Burnwal
(200101044)

Outline of Presentation
● Importance of Power Management in Embedded
Systems
● Approaches to Power Management
● Static & Dynamic Power Management
● Adaptive Device Power Management
● Dynamic Power Management in detail
● Conclusion

Importance of Power Management
● Applications of Embedded Devices increasing
day by day
● Users want more and more functionality in
smaller & smaller size and longer battery life
● Developments in Batteries have not kept pace
with those in Processing Power and Memory
Storage
● Result: Imbalance between battery requirements
and what can be fulfilled
● So, Power management is crucial to embedded
systems, since it determines operating time

How to Begin?
● Different Approach than Desktops & other devices
● Constraints: Battery, Processing Power, Memory, Cost
● Divide & Conquer: so that power can be efficiently
managed independently in those areas
● e.g. Processor, Memory, Display, Peripherals
● Today, Processors are already quite Power Efficient
● So, typically, we've to adopt System-Wide Power
Management Strategies
● e.g. In an embedded device with Colored LCD screen and
high performance memory, power consumption in
Processor is insignificant

Approaches to Power Management

Power Efficient Hardware & Software Design
● At Hardware Level:
– e.g. Intel Centrino Processors
● At Device Driver Level:
– e.g. Device driver to turn off/suspend the device after a
certain period of inactivity or increase polling interval
● At Application/Software Level:
– e.g. Monitor Refresh Rate can set by application
(Games: High, Other Usages: Low)
– e.g. Audio Playback Quality (Sampling Rate) can set
by application while recording (Music:high,Voice:low)

Static Power Management
● Deals with Regulating Power Consumption in inactive
periods while preserving the states of OS & Applications
according to pre-defined policies
● Require User action to reactivate the system
● e.g. Sleep, Hibernation & Suspend
● Commonly used in Desktops & Servers
● Also used to some extent in Handheld devices, mobile
phones, Digital Cameras, Laptops, PDAs etc

Dynamic Power Management
● DPM refers to Power Management schemes
implemented while programs are running
● Manage power of Peripheral Devices through
Device Drivers and Operating System
● e.g. Spinning down Disks when not in use
● Memory Controller System to reduce Power
● Discussed in detail by Udayan later in this
presentation

Recent Techniques: Hardware Level
● The following techniques reduce power consumption
at CMOS level
– Voltage Scaling
– Frequency Scaling (Clock Gating Methods)
● To Discuss this, we require some background
knowledge of CMOS

The CMOS Power Equation
● Total Power= Static/leakage Power + Dynamic Power +
Short Circuit Power
● P = V*I leak + 1/2*A*C*V 2 *f + A*V*I short
● P is the Power consumed at Supply Voltage- V
● I leak is the leakage current
● C is the total switched capacitance of the output node
● F if the operating frequency
● A is the switching activity factor (fraction of gates active
switching each clock)

Power Dissapation in a CMOS
● Two main sources of Power Dissapation in CMOS
– Static/Leakage Power Dissapation: Results from leakage
Current originating due to Resistive paths between Supply
Voltage and Ground. Currently it contributes 15-20% of power
dissapation at 130 nm technology. Exponentially increases as
chip technology moves ahead, below 100 nm
– Dynamic/Switching Power Dissapation: results from
switching capacitive loads between different Voltage levels i.e.
during clock transitions (largest component)
– Short Circuit Power Dissapation: due to short circuit current
when both transistors in a CMOS inverter are ON at the same
time. Negligibly small, so we concentrate on first two sources
of Power Dissapation

How to Reduce Power Consumption
at CMOS (Hardware) Design Level
● Reduce Static Power Consumption by reducing supply voltage
'V' and choosing the system design accordingly
● Reduce Dynamic Power Dissapation by reducing Supply
voltage 'V'
● Reduction of Operating Voltage: Voltage Scaling
● Reduction of Operating Frequency 'F': Frequency Scaling
● Reducing the switching coefficient of circuit 'A'
● Reducing the fraction of gates switching 'A' may not be
possible, as its primary purpose may not be solved
● Reducing the circuit load capacity, 'C'

Reducing Standby Power Consumption
● Use separate power supply for combinational &
sequential circuits [no power drawn by
combinational circuit during standby]
● Reduce power supply to combinational circuit
during standby ensuring that state is preserved
● Reducing V linearly reduces power

Dynamic Voltage Scaling
● Refers to runtime change in supply voltage levels
supplied to various components in a system so as
to reduce the overall system power dissapation
while maintaining constraints on time/throughput
● When operation at less than peak frequency is
permissible, frequency is lowered, followed by
reduction in voltage
● Significant power reduction as both f & V are
lowered

Relationship between Energy &
Frequency

Dynamic Power Management
Details

Dynamic Power Management
● Dynamic power management system that is only concerned with voltage
and frequency scaling the processor core may be of limited use.
Therefore we need a system wide Power Management Strategies.
● Predefined (generic) strategies may work in case of Large computing
devices. (e.g. built in hardware)
● However same Embedded system may require different strategies,
depending on the requirement.

Dynamic Power Management
● Aggressive power management. For example, scaling bus frequencies
can drive significant reductions in system-wide energy consumption.
[possible due to devices capable of quick transitions]
● Key observation is that the breakdown of system-wide energy consumption
as well as the most effective way to manage energy consumption
are highly application dependent. [example media player ]
● Dynamic power management architecture needs to be flexible enough
to support multiple platforms with differing requirements. Part of this
flexibility can be the pluggable power management policies support.

PC's and embedded devices
● In PC that the requirements for simplicity and flexibility are best
served by leaving the workings of the dynamic power management
system completely transparent to most tasks, and even to the
operating system itself. An implementation based on this proposal
need not require any changes to programs.
● In highly energy-constrained systems such as cellular phones,
however, task-specific dynamic power management is a hard
requirement. Architecture should support the ability of tasks to set
their own power-performance characteristics for those cases where
this is required. So applications must implement, power
management settings of its own.

Architectural Overview
● The strategy is communicated to
DPM in two ways:
1. as a predefined set of policies.
2. as an application/policy-set specific
policy manager that manages
them.

Policy & Policy Managers
● DPM policies are named data structures. Policies exert very fine-grained
control over the dynamic state of the system. Therefore, policies must be
installed into the operating system kernel for efficiency. Policies specify the
component and device-state transitions in line with the power management
strategy.
● DPM policy managers are executable programs that activate policies by
name. Policy managers implement user-defined or application-specific
power management strategies. Policy Manager should be flexible.

Policy Architecture – Operating
Point
● At any given point in time, a system is said to be executing at a particular
operating point. The operating point may be described by such parameters
as the core voltage, CPU and bus frequencies and the states of peripheral
devices.
●
● The operating point is the lowest-level object in the DPM system hierarchy.
An operating point object encapsulates the minimal set of inter-dependent,
physical and discrete parameters that define a specific system performance
level along with an associated energy cost. [inter-dependence b/w voltage
and frequency of a CPU core]
●
● A dynamic power management system could properly be defined as the set
of rules and procedures that move the system from one operating point to
another as events occur.

Operating State
● If a system supports multiple operating
points, some rules and mechanisms are
required to move the system from one
operating point to another.
● Current dynamic control mechanisms may
set operating points in response to changes
in activity or in response to the requests of
key programs.
● low latency of devices, scaling and
uninterrupted execution while changing
states, allows very fine-grain policies. Each
operating state may be associated with an
operating point specific to the requirements
of that state.

What DPM would not do.
● DPM would not manage the power usage of a device attached. These details
are left to the Device Driver.
For example, if a system is not currently producing or consuming audio data,
the device driver for the audio CODEC interface may power-down the
external CODEC chip as well as command the on-board clock and power
manager to remove the clock from the CODEC interface peripheral. From
the perspective of DPM, since the CODEC is a DMA peripheral these
changes alter the bandwidth (frequency) requirements for the on-board
peripheral bus, and it might be profitable to also trigger a change in the
operating point since the system is no longer constrained by the DMA
requirements of the audio subsystem.

Congruence Class
● No device driver has the global view of the system or the power
management strategy required to completely specify the operating point.
This information is centralized in the DPM policy structure as a
congruence class of operating points.
● Any of the operating points in a class would be acceptable as an operating
point for the system in the given operating state, although device constraints
might render some members of the class invalid, and power considerations
might cause one operating point to be preferred over other valid operating
points in the class. At any given point in time a valid DPM policy will
designate one member of each congruence class as the selected operating
point for that class.

Congruence Class
A class of operating
points is assigned to a
system state, e.g. task
or idle, and the
selected element of the
class is used when the
system is in that state.

Task
Example
operating points
operating state
LCD and security chip disabled
congruence class
Note : Security Chip requires EXT of 33 MHz
LCD requires PXL of 17 to 25 MHz
Idle

Example
LCD controller active, security chip disabled
Task Both LCD and security chip enabled Idle
Note : Security Chip requires EXT of 33 MHz
LCD requires PXL of 17 to 25 MHz

Implementation
● assert_constraint()
● remove_constraint()
● set_operating_state()
● set_policy()
● set_task_state()
required for Device
Drivers and Kernel
For user process

Conclusion
● Power is the most crucial resource in embedded systems [Why]
● Power management in Embedded Systems, which are driven by
constraints of battery power and scarce resources, is very differ-
ent from that used in Desktop environment.
● Power management in Embedded systems is highly application
and device specific and so no generic strategies can be applied
● Power management in Embedded systems calls for aggressive,
system-wide strategies.

References
● “Dynamic Power Management for Embedded Systems”
IBM & Monta Vista Software
● “Dynamic Power Management for Embedded Systems”
Bishop Brock & Karthick Rajmani
● OKI Technical Review
● “Power Optimization & Management in Embedded
Systems” Massoud Pedram, USC
● “Standby power reduction using Dynamic voltage
scaling” Calhoun & Chandrakasan, IEEE
● “Linux on eLap” David Gibson, IBM
● “Low power SOC for IBM's PowerPC” Gary Carpenter
● http://www.epn-online.com