Power Management in Embedded Systems - DAIICT Intranet
Power Management in Embedded Systems - DAIICT Intranet
Power Management in Embedded Systems - DAIICT Intranet
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<strong>Power</strong> <strong>Management</strong> <strong>in</strong><br />
<strong>Embedded</strong> <strong>Systems</strong><br />
Udayan Kumar<br />
(200101227)<br />
Kundan Burnwal<br />
(200101044)
Outl<strong>in</strong>e of Presentation<br />
● Importance of <strong>Power</strong> <strong>Management</strong> <strong>in</strong> <strong>Embedded</strong><br />
<strong>Systems</strong><br />
● Approaches to <strong>Power</strong> <strong>Management</strong><br />
● Static & Dynamic <strong>Power</strong> <strong>Management</strong><br />
● Adaptive Device <strong>Power</strong> <strong>Management</strong><br />
● Dynamic <strong>Power</strong> <strong>Management</strong> <strong>in</strong> detail<br />
● Conclusion
Importance of <strong>Power</strong> <strong>Management</strong><br />
● Applications of <strong>Embedded</strong> Devices <strong>in</strong>creas<strong>in</strong>g<br />
day by day<br />
● Users want more and more functionality <strong>in</strong><br />
smaller & smaller size and longer battery life<br />
● Developments <strong>in</strong> Batteries have not kept pace<br />
with those <strong>in</strong> Process<strong>in</strong>g <strong>Power</strong> and Memory<br />
Storage<br />
● Result: Imbalance between battery requirements<br />
and what can be fulfilled<br />
● So, <strong>Power</strong> management is crucial to embedded<br />
systems, s<strong>in</strong>ce it determ<strong>in</strong>es operat<strong>in</strong>g time
How to Beg<strong>in</strong>?<br />
● Different Approach than Desktops & other devices<br />
● Constra<strong>in</strong>ts: Battery, Process<strong>in</strong>g <strong>Power</strong>, Memory, Cost<br />
● Divide & Conquer: so that power can be efficiently<br />
managed <strong>in</strong>dependently <strong>in</strong> those areas<br />
● e.g. Processor, Memory, Display, Peripherals<br />
● Today, Processors are already quite <strong>Power</strong> Efficient<br />
● So, typically, we've to adopt System-Wide <strong>Power</strong><br />
<strong>Management</strong> Strategies<br />
● e.g. In an embedded device with Colored LCD screen and<br />
high performance memory, power consumption <strong>in</strong><br />
Processor is <strong>in</strong>significant
Approaches to <strong>Power</strong> <strong>Management</strong>
<strong>Power</strong> Efficient Hardware & Software Design<br />
● At Hardware Level:<br />
– e.g. Intel Centr<strong>in</strong>o Processors<br />
● At Device Driver Level:<br />
– e.g. Device driver to turn off/suspend the device after a<br />
certa<strong>in</strong> period of <strong>in</strong>activity or <strong>in</strong>crease poll<strong>in</strong>g <strong>in</strong>terval<br />
● At Application/Software Level:<br />
– e.g. Monitor Refresh Rate can set by application<br />
(Games: High, Other Usages: Low)<br />
– e.g. Audio Playback Quality (Sampl<strong>in</strong>g Rate) can set<br />
by application while record<strong>in</strong>g (Music:high,Voice:low)
Static <strong>Power</strong> <strong>Management</strong><br />
● Deals with Regulat<strong>in</strong>g <strong>Power</strong> Consumption <strong>in</strong> <strong>in</strong>active<br />
periods while preserv<strong>in</strong>g the states of OS & Applications<br />
accord<strong>in</strong>g to pre-def<strong>in</strong>ed policies<br />
● Require User action to reactivate the system<br />
● e.g. Sleep, Hibernation & Suspend<br />
● Commonly used <strong>in</strong> Desktops & Servers<br />
● Also used to some extent <strong>in</strong> Handheld devices, mobile<br />
phones, Digital Cameras, Laptops, PDAs etc
Dynamic <strong>Power</strong> <strong>Management</strong><br />
● DPM refers to <strong>Power</strong> <strong>Management</strong> schemes<br />
implemented while programs are runn<strong>in</strong>g<br />
● Manage power of Peripheral Devices through<br />
Device Drivers and Operat<strong>in</strong>g System<br />
● e.g. Sp<strong>in</strong>n<strong>in</strong>g down Disks when not <strong>in</strong> use<br />
● Memory Controller System to reduce <strong>Power</strong><br />
● Discussed <strong>in</strong> detail by Udayan later <strong>in</strong> this<br />
presentation
Recent Techniques: Hardware Level<br />
● The follow<strong>in</strong>g techniques reduce power consumption<br />
at CMOS level<br />
– Voltage Scal<strong>in</strong>g<br />
– Frequency Scal<strong>in</strong>g (Clock Gat<strong>in</strong>g Methods)<br />
● To Discuss this, we require some background<br />
knowledge of CMOS
The CMOS <strong>Power</strong> Equation<br />
● Total <strong>Power</strong>= Static/leakage <strong>Power</strong> + Dynamic <strong>Power</strong> +<br />
Short Circuit <strong>Power</strong><br />
● P = V*I leak + 1/2*A*C*V 2 *f + A*V*I short<br />
● P is the <strong>Power</strong> consumed at Supply Voltage- V<br />
● I leak is the leakage current<br />
● C is the total switched capacitance of the output node<br />
● F if the operat<strong>in</strong>g frequency<br />
● A is the switch<strong>in</strong>g activity factor (fraction of gates active<br />
switch<strong>in</strong>g each clock)
<strong>Power</strong> Dissapation <strong>in</strong> a CMOS<br />
● Two ma<strong>in</strong> sources of <strong>Power</strong> Dissapation <strong>in</strong> CMOS<br />
– Static/Leakage <strong>Power</strong> Dissapation: Results from leakage<br />
Current orig<strong>in</strong>at<strong>in</strong>g due to Resistive paths between Supply<br />
Voltage and Ground. Currently it contributes 15-20% of power<br />
dissapation at 130 nm technology. Exponentially <strong>in</strong>creases as<br />
chip technology moves ahead, below 100 nm<br />
– Dynamic/Switch<strong>in</strong>g <strong>Power</strong> Dissapation: results from<br />
switch<strong>in</strong>g capacitive loads between different Voltage levels i.e.<br />
dur<strong>in</strong>g clock transitions (largest component)<br />
– Short Circuit <strong>Power</strong> Dissapation: due to short circuit current<br />
when both transistors <strong>in</strong> a CMOS <strong>in</strong>verter are ON at the same<br />
time. Negligibly small, so we concentrate on first two sources<br />
of <strong>Power</strong> Dissapation
How to Reduce <strong>Power</strong> Consumption<br />
at CMOS (Hardware) Design Level<br />
● Reduce Static <strong>Power</strong> Consumption by reduc<strong>in</strong>g supply voltage<br />
'V' and choos<strong>in</strong>g the system design accord<strong>in</strong>gly<br />
● Reduce Dynamic <strong>Power</strong> Dissapation by reduc<strong>in</strong>g Supply<br />
voltage 'V'<br />
● Reduction of Operat<strong>in</strong>g Voltage: Voltage Scal<strong>in</strong>g<br />
● Reduction of Operat<strong>in</strong>g Frequency 'F': Frequency Scal<strong>in</strong>g<br />
● Reduc<strong>in</strong>g the switch<strong>in</strong>g coefficient of circuit 'A'<br />
● Reduc<strong>in</strong>g the fraction of gates switch<strong>in</strong>g 'A' may not be<br />
possible, as its primary purpose may not be solved<br />
● Reduc<strong>in</strong>g the circuit load capacity, 'C'
Reduc<strong>in</strong>g Standby <strong>Power</strong> Consumption<br />
● Use separate power supply for comb<strong>in</strong>ational &<br />
sequential circuits [no power drawn by<br />
comb<strong>in</strong>ational circuit dur<strong>in</strong>g standby]<br />
● Reduce power supply to comb<strong>in</strong>ational circuit<br />
dur<strong>in</strong>g standby ensur<strong>in</strong>g that state is preserved<br />
● Reduc<strong>in</strong>g V l<strong>in</strong>early reduces power
Dynamic Voltage Scal<strong>in</strong>g<br />
● Refers to runtime change <strong>in</strong> supply voltage levels<br />
supplied to various components <strong>in</strong> a system so as<br />
to reduce the overall system power dissapation<br />
while ma<strong>in</strong>ta<strong>in</strong><strong>in</strong>g constra<strong>in</strong>ts on time/throughput<br />
● When operation at less than peak frequency is<br />
permissible, frequency is lowered, followed by<br />
reduction <strong>in</strong> voltage<br />
● Significant power reduction as both f & V are<br />
lowered
Relationship between Energy &<br />
Frequency
Dynamic <strong>Power</strong> <strong>Management</strong><br />
Details
Dynamic <strong>Power</strong> <strong>Management</strong><br />
● Dynamic power management system that is only concerned with voltage<br />
and frequency scal<strong>in</strong>g the processor core may be of limited use.<br />
Therefore we need a system wide <strong>Power</strong> <strong>Management</strong> Strategies.<br />
● Predef<strong>in</strong>ed (generic) strategies may work <strong>in</strong> case of Large comput<strong>in</strong>g<br />
devices. (e.g. built <strong>in</strong> hardware)<br />
● However same <strong>Embedded</strong> system may require different strategies,<br />
depend<strong>in</strong>g on the requirement.
Dynamic <strong>Power</strong> <strong>Management</strong><br />
● Aggressive power management. For example, scal<strong>in</strong>g bus frequencies<br />
can drive significant reductions <strong>in</strong> system-wide energy consumption.<br />
[possible due to devices capable of quick transitions]<br />
● Key observation is that the breakdown of system-wide energy consumption<br />
as well as the most effective way to manage energy consumption<br />
are highly application dependent. [example media player ]<br />
● Dynamic power management architecture needs to be flexible enough<br />
to support multiple platforms with differ<strong>in</strong>g requirements. Part of this<br />
flexibility can be the pluggable power management policies support.
PC's and embedded devices<br />
● In PC that the requirements for simplicity and flexibility are best<br />
served by leav<strong>in</strong>g the work<strong>in</strong>gs of the dynamic power management<br />
system completely transparent to most tasks, and even to the<br />
operat<strong>in</strong>g system itself. An implementation based on this proposal<br />
need not require any changes to programs.<br />
● In highly energy-constra<strong>in</strong>ed systems such as cellular phones,<br />
however, task-specific dynamic power management is a hard<br />
requirement. Architecture should support the ability of tasks to set<br />
their own power-performance characteristics for those cases where<br />
this is required. So applications must implement, power<br />
management sett<strong>in</strong>gs of its own.
Architectural Overview<br />
● The strategy is communicated to<br />
DPM <strong>in</strong> two ways:<br />
1. as a predef<strong>in</strong>ed set of policies.<br />
2. as an application/policy-set specific<br />
policy manager that manages<br />
them.
Policy & Policy Managers<br />
● DPM policies are named data structures. Policies exert very f<strong>in</strong>e-gra<strong>in</strong>ed<br />
control over the dynamic state of the system. Therefore, policies must be<br />
<strong>in</strong>stalled <strong>in</strong>to the operat<strong>in</strong>g system kernel for efficiency. Policies specify the<br />
component and device-state transitions <strong>in</strong> l<strong>in</strong>e with the power management<br />
strategy.<br />
● DPM policy managers are executable programs that activate policies by<br />
name. Policy managers implement user-def<strong>in</strong>ed or application-specific<br />
power management strategies. Policy Manager should be flexible.
Policy Architecture – Operat<strong>in</strong>g<br />
Po<strong>in</strong>t<br />
● At any given po<strong>in</strong>t <strong>in</strong> time, a system is said to be execut<strong>in</strong>g at a particular<br />
operat<strong>in</strong>g po<strong>in</strong>t. The operat<strong>in</strong>g po<strong>in</strong>t may be described by such parameters<br />
as the core voltage, CPU and bus frequencies and the states of peripheral<br />
devices.<br />
●<br />
● The operat<strong>in</strong>g po<strong>in</strong>t is the lowest-level object <strong>in</strong> the DPM system hierarchy.<br />
An operat<strong>in</strong>g po<strong>in</strong>t object encapsulates the m<strong>in</strong>imal set of <strong>in</strong>ter-dependent,<br />
physical and discrete parameters that def<strong>in</strong>e a specific system performance<br />
level along with an associated energy cost. [<strong>in</strong>ter-dependence b/w voltage<br />
and frequency of a CPU core]<br />
●<br />
● A dynamic power management system could properly be def<strong>in</strong>ed as the set<br />
of rules and procedures that move the system from one operat<strong>in</strong>g po<strong>in</strong>t to<br />
another as events occur.
Operat<strong>in</strong>g State<br />
● If a system supports multiple operat<strong>in</strong>g<br />
po<strong>in</strong>ts, some rules and mechanisms are<br />
required to move the system from one<br />
operat<strong>in</strong>g po<strong>in</strong>t to another.<br />
● Current dynamic control mechanisms may<br />
set operat<strong>in</strong>g po<strong>in</strong>ts <strong>in</strong> response to changes<br />
<strong>in</strong> activity or <strong>in</strong> response to the requests of<br />
key programs.<br />
● low latency of devices, scal<strong>in</strong>g and<br />
un<strong>in</strong>terrupted execution while chang<strong>in</strong>g<br />
states, allows very f<strong>in</strong>e-gra<strong>in</strong> policies. Each<br />
operat<strong>in</strong>g state may be associated with an<br />
operat<strong>in</strong>g po<strong>in</strong>t specific to the requirements<br />
of that state.
What DPM would not do.<br />
● DPM would not manage the power usage of a device attached. These details<br />
are left to the Device Driver.<br />
For example, if a system is not currently produc<strong>in</strong>g or consum<strong>in</strong>g audio data,<br />
the device driver for the audio CODEC <strong>in</strong>terface may power-down the<br />
external CODEC chip as well as command the on-board clock and power<br />
manager to remove the clock from the CODEC <strong>in</strong>terface peripheral. From<br />
the perspective of DPM, s<strong>in</strong>ce the CODEC is a DMA peripheral these<br />
changes alter the bandwidth (frequency) requirements for the on-board<br />
peripheral bus, and it might be profitable to also trigger a change <strong>in</strong> the<br />
operat<strong>in</strong>g po<strong>in</strong>t s<strong>in</strong>ce the system is no longer constra<strong>in</strong>ed by the DMA<br />
requirements of the audio subsystem.
Congruence Class<br />
● No device driver has the global view of the system or the power<br />
management strategy required to completely specify the operat<strong>in</strong>g po<strong>in</strong>t.<br />
This <strong>in</strong>formation is centralized <strong>in</strong> the DPM policy structure as a<br />
congruence class of operat<strong>in</strong>g po<strong>in</strong>ts.<br />
● Any of the operat<strong>in</strong>g po<strong>in</strong>ts <strong>in</strong> a class would be acceptable as an operat<strong>in</strong>g<br />
po<strong>in</strong>t for the system <strong>in</strong> the given operat<strong>in</strong>g state, although device constra<strong>in</strong>ts<br />
might render some members of the class <strong>in</strong>valid, and power considerations<br />
might cause one operat<strong>in</strong>g po<strong>in</strong>t to be preferred over other valid operat<strong>in</strong>g<br />
po<strong>in</strong>ts <strong>in</strong> the class. At any given po<strong>in</strong>t <strong>in</strong> time a valid DPM policy will<br />
designate one member of each congruence class as the selected operat<strong>in</strong>g<br />
po<strong>in</strong>t for that class.
Congruence Class<br />
A class of operat<strong>in</strong>g<br />
po<strong>in</strong>ts is assigned to a<br />
system state, e.g. task<br />
or idle, and the<br />
selected element of the<br />
class is used when the<br />
system is <strong>in</strong> that state.
Task<br />
Example<br />
operat<strong>in</strong>g po<strong>in</strong>ts<br />
operat<strong>in</strong>g state<br />
LCD and security chip disabled<br />
congruence class<br />
Note : Security Chip requires EXT of 33 MHz<br />
LCD requires PXL of 17 to 25 MHz<br />
Idle
Example<br />
LCD controller active, security chip disabled<br />
Task Both LCD and security chip enabled Idle<br />
Note : Security Chip requires EXT of 33 MHz<br />
LCD requires PXL of 17 to 25 MHz
Implementation<br />
● assert_constra<strong>in</strong>t()<br />
● remove_constra<strong>in</strong>t()<br />
● set_operat<strong>in</strong>g_state()<br />
● set_policy()<br />
● set_task_state()<br />
required for Device<br />
Drivers and Kernel<br />
For user process
Conclusion<br />
● <strong>Power</strong> is the most crucial resource <strong>in</strong> embedded systems [Why]<br />
● <strong>Power</strong> management <strong>in</strong> <strong>Embedded</strong> <strong>Systems</strong>, which are driven by<br />
constra<strong>in</strong>ts of battery power and scarce resources, is very differ-<br />
ent from that used <strong>in</strong> Desktop environment.<br />
● <strong>Power</strong> management <strong>in</strong> <strong>Embedded</strong> systems is highly application<br />
and device specific and so no generic strategies can be applied<br />
● <strong>Power</strong> management <strong>in</strong> <strong>Embedded</strong> systems calls for aggressive,<br />
system-wide strategies.
References<br />
● “Dynamic <strong>Power</strong> <strong>Management</strong> for <strong>Embedded</strong> <strong>Systems</strong>”<br />
IBM & Monta Vista Software<br />
● “Dynamic <strong>Power</strong> <strong>Management</strong> for <strong>Embedded</strong> <strong>Systems</strong>”<br />
Bishop Brock & Karthick Rajmani<br />
● OKI Technical Review<br />
● “<strong>Power</strong> Optimization & <strong>Management</strong> <strong>in</strong> <strong>Embedded</strong><br />
<strong>Systems</strong>” Massoud Pedram, USC<br />
● “Standby power reduction us<strong>in</strong>g Dynamic voltage<br />
scal<strong>in</strong>g” Calhoun & Chandrakasan, IEEE<br />
● “L<strong>in</strong>ux on eLap” David Gibson, IBM<br />
● “Low power SOC for IBM's <strong>Power</strong>PC” Gary Carpenter<br />
● http://www.epn-onl<strong>in</strong>e.com