AMD SB700/710/750 Register Programming Requirements
AMD SB700/710/750 Register Programming Requirements
AMD SB700/710/750 Register Programming Requirements
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5.5 Master Latency Timer<br />
ASIC REV <strong>Register</strong> Settings Function/Comment<br />
All Revs SB7x0 PCIB_PCI_config 0x0D = 0x40 (default)<br />
PCIB_PCI_config 0x1B = 0x40 (default)<br />
SATA USB SMBUS PATA AC97 HD AUDIO LPC PCI<br />
X<br />
RTC ACPI PM REG A-LINK I/O REG XIOAPIC<br />
5.6 DMA Read Command Match<br />
Enables the PCIB to retain ownership of the bus on the<br />
Primary side and on the Secondary side when GNT# is deasserted.<br />
Note: This setting is mandatory.<br />
ASIC REV <strong>Register</strong> Settings Function/Comment<br />
All Revs SB7x0 PCIB_PCI_config 0x4B[6] = 1 (default)<br />
SATA USB SMBUS PATA AC97 HD AUDIO LPC PCI<br />
X<br />
RTC ACPI PM REG A-LINK I/O REG XIOAPIC<br />
5.7 Enabling Idle To GNT# Check<br />
For register details, refer to<br />
the sections check-marked<br />
in the <strong>SB700</strong>/<strong>710</strong>/<strong>750</strong><br />
<strong>Register</strong> Reference Guide.<br />
Enables the command matching checking function on<br />
“Memory Read” & “Memory Read Line” commands.<br />
Some PCI devices may change the “Memory read<br />
command” to “Memory read line” command before the data<br />
is completed. This bit enables the command matching<br />
checking inside the PCIB to work with this kind of device.<br />
Note: This setting is mandatory.<br />
ASIC REV <strong>Register</strong> Settings Function/Comment<br />
All Revs SB7x0 PCIB_PCI_config 0x4B [0] = 1 (default)<br />
SATA USB SMBUS PATA AC97 HD AUDIO LPC PCI<br />
X<br />
RTC ACPI PM REG A-LINK I/O REG XIOAPIC<br />
5.8 GNT# Timing Adjustment<br />
For register details, refer to<br />
the sections check-marked<br />
in the <strong>SB700</strong>/<strong>710</strong>/<strong>750</strong><br />
<strong>Register</strong> Reference Guide.<br />
When enabled, the PCI arbiter checks for the Bus Idle<br />
before asserting GNT#.<br />
Note: This setting is recommended.<br />
ASIC REV <strong>Register</strong> Settings Function/Comment<br />
All Revs SB7x0 PCIB_PCI_config 0x64 [12] = 1 (default)<br />
Adjusts the GNT# de-assertion time.<br />
Note: This setting is recommended.<br />
SATA USB SMBUS PATA AC97 HD AUDIO LPC PCI<br />
X<br />
RTC ACPI PM REG A-LINK I/O REG XIOAPIC<br />
For register details, refer to<br />
the sections check-marked<br />
in the <strong>SB700</strong>/<strong>710</strong>/<strong>750</strong><br />
<strong>Register</strong> Reference Guide.<br />
For register details, refer to<br />
the sections check-marked<br />
in the <strong>SB700</strong>/<strong>710</strong>/<strong>750</strong><br />
<strong>Register</strong> Reference Guide.<br />
© 2009 Advanced Micro Devices, Inc. PCIB (PCI-bridge, bus-0, dev-20, fun-04)<br />
<strong>AMD</strong> <strong>SB700</strong>/<strong>710</strong>/<strong>750</strong> <strong>Register</strong> <strong>Programming</strong> <strong>Requirements</strong> Page 40
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