AMD SB700/710/750 Register Programming Requirements

6.14 Enabling Fix to Cover the Corner Case S3 Wake Up Issue
ASIC Rev Register Settings Function/Comment
SB7x0 A12 OHCI 0_PCI_Config 0x50[16] = 1 Enables the fix to cover the corner case S3 wake up issue
seen with some specific USB 1.1 keyboards.
SATA USB SMBUS PATA AC97 HD AUDIO LPC PCI
X
RTC ACPI PM REG A-LINK I/O REG XIOAPIC
6.15 EHCI Async Park Mode
(See section 6.20)
6.16 MSI Feature in USB 2.0 Controller
ASIC Rev Register Settings Function/Comment
All Revs SB7x0 EHCI_PCI_Config 0x50[6] = 1
SATA USB SMBUS PATA AC97 HD AUDIO LPC PCI
X
RTC ACPI PM REG A-LINK I/O REG XIOAPIC
6.17 EHCI Dynamic Clock Gating Feature
For register details, refer to
the sections check-marked
in the SB700/710/750
Register Reference Guide.
MSI function
For normal operation the MSI function should be disabled
by setting the bit in both EHCI controllers.
Bus-0, dev-18 fun 2 and Bus 0 dev-19 fun-2
ASIC Rev Register Settings Function/Comment
All Revs SB7x0 EHCI_BAR 0xBC Bit[12] = 0
For register details, refer to
the sections check-marked
in the SB700/710/750
Register Reference Guide.
For normal operation, the clock gating feature must be
disabled. At system reset, this bit is set to “1”. So, BIOS
needs to program this bit to “0”.
EHCI clock gating setting must be programmed in both the
EHCI host controllers.
Bus-0, dev-18 fun 2 and Bus 0 dev-19 fun-2
A BIOS workaround is required to disable the EHCI Dynamic clock gating on resume from S5/S4. See Sample Code A1 in
Appendix A for sample code of this workaround.
SATA USB SMBUS PATA AC97 HD AUDIO LPC PCI
X
RTC ACPI PM REG A-LINK I/O REG XIOAPIC
For register details, refer to
the sections check-marked
in the SB700/710/750
Register Reference Guide.
© 2009 Advanced Micro Devices, Inc. USB – OHCI & EHCI Controllers (bus-0, dev-18/19, fun-00 ~02/
bus-0, dev-20, fun-05)
AMD SB700/710/750 Register Programming Requirements Page 48