AMD SB700/710/750 Register Programming Requirements

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1.2 AMD SB700 Block Diagram This section contains a block diagram for the SB700. Figure 1 below shows the SB7x0 internal PCI devices and major function blocks. Figure 1 SB7x0 Internal PCI Devices and Major Function Blocks © 2009 Advanced Micro Devices, Inc. Introduction AMD SB700/710/750 Register Programming Requirements Page 8
1.3 Register Reference Information Tables within this document contain information showing the applicable revision, recommended settings, and comments associated with the register. Consider the following example: ASIC Rev Register Settings Function/Comment All Revs SB7x0 PM_IO 0x52[5:0] = 08h Recommended Delay for S3/S4/S5 resume sequence SATA USB SMBUS PATA AC97 HD AUDIO LPC PCI RTC ACPI PM REG A-LINK I/O REG XIOAPIC X For register details, refer to the sections check-marked in the SB700/710/ 750 Register Reference Guide. • ASIC Rev: o “All Revs SB7x0” = Applicable to all revisions of the SB700, SB710, and SB750 o “SB7x0 A12” = Applicable to the SB700, and revision A12 of the SB710 and SB750 o “SB7x0 A14” or SB7x0 A14 and above = Applicable to revision A14 of the SB710 and SB750, and revisions A14 and A15 of the SP5100 • Register Settings: Recommended register setting, with the register name. For more detailed information about the registers found within this document, refer to the AMD SB700/710/750 Register Reference Guide (43009). The applicable sections in the register reference guide where the information can be found are marked with “x” in the tables in this document. © 2009 Advanced Micro Devices, Inc. Introduction AMD SB700/710/750 Register Programming Requirements Page 9
Page 1 and 2: AMD SB700/710/750 Register Programm
Page 3 and 4: Table of Contents 1 Introduction ..
Page 5 and 6: 6.1 Enabling/Disabling OHCI and EHC
Page 7: 1 Introduction 1.1 About This Manua
Page 11 and 12: ASIC Rev Register Settings Function
Page 13 and 14: 2.5 Enabling Non-Posted Memory Writ
Page 15 and 16: All Revs SB7x0 USB HC(bus0, dev 19,
Page 17 and 18: 2.16 PCIE Native Mode ASIC Rev Regi
Page 19 and 20: 2.21 CPU Reset ASIC Rev Register Se
Page 21 and 22: StatusMask0- RW - 8 bits - [ASF_IO:
Page 23 and 24: SlaveAddress- RW - 8 bits - [ASF_IO
Page 25 and 26: • Step 3: Program the ListenAdr t
Page 27 and 28: 2.26 ACPI System Clock Setting ASIC
Page 29 and 30: SB7x0 A14 and above PMIO 0xD7[0] =
Page 31 and 32: 3 LPC Controller (bus-0, dev-20, fu
Page 33 and 34: 4.3 Enabling Upstream DMA Access AS
Page 35 and 36: 4.9 Enabling Detection of Upstream
Page 37 and 38: 4.16 SMI IO Write ASIC Rev Register
Page 39 and 40: 5 PCIB (PCI-bridge, bus-0, dev-20,
Page 41 and 42: 5.9 Enabling Fast Back to Back Retr
Page 43 and 44: 6 USB - OHCI & EHCI Controllers (bu
Page 45 and 46: 6.5 USB Reset Sequence ASIC Rev Reg
Page 47 and 48: 6.10 OHCI MSI Function Setting ASIC
Page 49 and 50: 6.18 USB 1.1 ISO OUT Devices/Speake
Page 51 and 52: SB7x0 A14 and above EHCI_PCI_Config
Page 53 and 54: ASIC Rev Register Settings Function
Page 55 and 56: 7.5 SATA Subclass Programming Seque
Page 57 and 58: 7.7 SATA Identification Programming
Page 59 and 60:
7.9 Internal and External SATA Port
Page 61 and 62:
© 2009 Advanced Micro Devices, Inc
Page 63 and 64:
7.12 Disabling CCC (Command Complet
Page 65 and 66:
9 IDE Controller (bus-0, dev-20, fu
Page 67 and 68:
10.4 Monitoring PwrGood on Sleep De
Page 69 and 70:
10.10 Disabling Pull-ups and Pull-d
Page 71 and 72:
10.14 EC Enhanced Mode - LPC ASIC R
Page 73 and 74:
ASIC Rev Register Settings Function
Page 75 and 76:
mov eax, 080009210h mov dx, 0CF8h o
Page 77 and 78:
A2. Sample Code for SB7x0 Erratum #
Page 79:
Appendix B: Revision History Date R
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AMD SB700/710/750 Register Programming Requirements

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