uPSD3434EB40U6

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Summary description uPSD34xx 10/293 Figure 2. Block Diagram P3.0:7 P1.0:7 P4.0:7 USB+, USB– (3) 16-bit Timer/ Counters (2) External Interrupts I 2 C Turbo 8032 Core UART0 (8) GPIO, Port 3 (8) GPIO, Port 1 (8) 10-bit ADC Optional IrDA Encoder/Decoder SPI (8) GPIO, Port 4 USB v2.0, Full Speed PFQ & BC UART1 16-bit PCA (6) PWM, CAPCOM, TIMER 10 FIFOs uPSD34xx SYSTEM BUS Programmable Decode and Page Logic General Purpose Programmable Logic, 16 Macrocells 1st Flash Memory: 64K, 128K, or 256K Bytes 2nd Flash Memory: 32K Bytes SRAM: 4K, 8K or 32K Bytes JTAG ICE and ISP (8) GPIO, Port A (80-pin only) (8) GPIO, Port B (2) GPIO, Port D (4) GPIO, Port C 8032 Address/Data/Control Bus (80-pin device only) Supervisor: Watchdog and Low-Voltage Reset V CC , V DD , GND, Reset, Crystal In PA0:7 PB0:7 PD1:2 PC0:7 MCU Bus Dedicated Pins AI09695b
uPSD34xx Pin descriptions 2 Pin descriptions Figure 3. TQFP52 connections PD1/CLKIN 1 PC7 2 JTAG TDO 3 JTAG TDI 4 DEBUG 5 3.3V VCC 6 USB+ 7 V (1) DD 8 GND 9 USB– 10 PC2/VSTBY 11 JTAG TCK 12 JTAG TMS 13 PB0 PB1 52 51 14 15 SPISEL (2) /PCACLK1/P4.7 SPITXD (2) /TCM5/P4.6 PB2 PB3 50 49 16 17 SPIRXD (2) /TCM4/P4.5 SPICLK (2) /TCM3/P4.4 39 P1.5/SPIRXD (2) /ADC5 38 P1.4/SPICLK (2) /ADC4 37 P1.3/TXD1(IrDA) (2) /ADC3 36 P1.2/RXD1(IrDA) (2) /ADC2 35 P1.1/T2X (2) /ADC1 34 P1.0/T2 (2) /ADC0 33 V (1) DD 32 XTAL2 31 XTAL1 30 P3.7/SCL 29 P3.6/SDA 28 P3.5/C1 27 P3.4/C0 Note: 1 For 5V applications, VDD must be connected to a 5.0V source. For 3.3V applications, VDD must be connected to a 3.3V source. 2 These signals can be used on one of two different ports (Port 1 or Port 4) for flexibility. Default is Port1. 3 AVREF and 3.3V AVCC are shared in the 52-pin package only. ADC channels must use 3.3V as AVREF for the 52-pin package. PB4 AVCC /AV (3) REF 48 47 18 19 TXD1(IrDA) (2) /PCACLK0/P4.3 GND PB5 GND RESET_IN PB6 PB7 P1.7/SPISEL (2) /ADC7 46 45 20 21 44 43 22 23 RXD1(IrDA) (2) /TCM2/P4.2 T2X (2) /TCM1/P4.1 T2 (2) /TCM0/P4.0 RXD0/P3.0 TXD0/P3.1 42 41 24 25 P1.6/SPITXD (2) /ADC6 40 26 EXTINT0/TG0/P3.2 EXTINT1/TG1/P3.3 AI09696b 11/293
Page 1 and 2: Features summary uPSD34xx Turbo Plu
Page 3 and 4: uPSD34xx Contents Contents 1 Summar
Page 5 and 6: uPSD34xx Contents 18.3 Connecting e
Page 7 and 8: uPSD34xx Contents 27.5 Timer mode .
Page 9: uPSD34xx Summary description 1 Summ
Page 13 and 14: uPSD34xx Pin descriptions Table 2.
Page 15 and 16: uPSD34xx Pin descriptions Table 2.
Page 17 and 18: uPSD34xx Hardware description 3 Har
Page 19 and 20: uPSD34xx Memory organization 4 Memo
Page 21 and 22: uPSD34xx Memory organization 4.2.1
Page 23 and 24: uPSD34xx 8032 MCU core performance
Page 25 and 26: uPSD34xx 8032 MCU core performance
Page 27 and 28: uPSD34xx MCU module description 6 M
Page 29 and 30: uPSD34xx 8032 MCU registers the B R
Page 31 and 32: uPSD34xx Special function registers
Page 39 and 40: uPSD34xx 8032 addressing modes 9.4
Page 41 and 42: uPSD34xx 8032 addressing modes addr
Page 43 and 44: uPSD34xx uPSD34xx instruction set s
Page 45 and 46: uPSD34xx uPSD34xx instruction set s
Page 47 and 48: uPSD34xx Dual data pointers 11 Dual
Page 49 and 50: uPSD34xx Dual data pointers LOOP: M
Page 51 and 52: uPSD34xx Debug unit up to VCC as de
Page 53 and 54: uPSD34xx Interrupt system If an int
Page 55 and 56: uPSD34xx Interrupt system 13.1 Indi
Page 57 and 58: uPSD34xx Interrupt system Table 18.
Page 59 and 60: uPSD34xx MCU clock generation 14 MC
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uPSD34xx MCU clock generation Figur
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uPSD34xx Power saving modes 15 Powe
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uPSD34xx Power saving modes Table 2
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uPSD34xx Oscillator and external co
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uPSD34xx I/O ports of mcu module 17
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uPSD34xx I/O ports of mcu module CP
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uPSD34xx I/O ports of mcu module Ta
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uPSD34xx I/O ports of mcu module ou
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uPSD34xx I/O ports of mcu module Ta
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uPSD34xx MCU bus interface A[10:8]
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uPSD34xx MCU bus interface Table 37
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uPSD34xx Supervisory functions 19 S
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uPSD34xx Supervisory functions To p
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uPSD34xx Standard 8032 timer/counte
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uPSD34xx Serial UART interfaces 21
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uPSD34xx Serial UART interfaces SM2
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uPSD34xx Serial UART interfaces 21.
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uPSD34xx Serial UART interfaces Fig
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uPSD34xx IrDA interface 22 IrDA int
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uPSD34xx IrDA interface Table 51. B
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uPSD34xx I 2 C interface 23 I 2 C i
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uPSD34xx I 2 C interface A few thin
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uPSD34xx I 2 C interface 23.6 Gener
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uPSD34xx I 2 C interface 23.8 I 2 C
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uPSD34xx I 2 C interface Table 56.
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uPSD34xx I 2 C interface 23.12 I 2
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uPSD34xx I 2 C interface Table 62.
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uPSD34xx I 2 C interface Set global
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uPSD34xx I 2 C interface Else If mo
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uPSD34xx I 2 C interface Does statu
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uPSD34xx SPI (synchronous periphera
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uPSD34xx USB interface 25 USB inter
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uPSD34xx USB interface 25.1.2 Endpo
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uPSD34xx USB interface 25.2 Types o
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uPSD34xx USB interface Figure 53. C
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uPSD34xx USB interface Figure 54. F
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uPSD34xx USB interface Command Valu
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uPSD34xx USB interface Table 70. US
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uPSD34xx USB interface ● USB IN F
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uPSD34xx USB interface ● USB Glob
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uPSD34xx USB interface ● USB OUT
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uPSD34xx USB interface ● USB Cont
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uPSD34xx USB interface ● USB Endp
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uPSD34xx USB interface Bit Symbol R
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uPSD34xx USB interface ● USB Setu
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uPSD34xx Analog-to-digital converto
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uPSD34xx Analog-to-digital converto
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uPSD34xx Programmable counter array
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uPSD34xx PSD module 28 PSD module T
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uPSD34xx PSD module 28.1.5 SRAM pro
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uPSD34xx PSD module 28.1.11 OMCs sm
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uPSD34xx PSD module 28.1.16 Power m
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uPSD34xx PSD module Table 103. HDL
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uPSD34xx PSD module Figure 67. Mapp
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uPSD34xx PSD module 28.2.7 The VM r
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uPSD34xx PSD module Note: x = NA Th
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uPSD34xx PSD module Register Name P
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uPSD34xx PSD module Table 107. Flas
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uPSD34xx PSD module 28.5.7 Toggle f
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uPSD34xx PSD module attempted to pr
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uPSD34xx PSD module indicate when a
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uPSD34xx PSD module If a Suspend Se
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uPSD34xx PSD module The DPLD perfor
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uPSD34xx PSD module Figure 74. DPLD
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uPSD34xx PSD module Figure 75. DPLD
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uPSD34xx PSD module 28.5.28 Output
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uPSD34xx PSD module Native product
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uPSD34xx PSD module 28.5.32 OMC mas
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uPSD34xx PSD module 28.5.34 I/O por
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uPSD34xx PSD module Port Operating
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uPSD34xx PSD module Table 126. MCU
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uPSD34xx PSD module After PSDsoft E
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uPSD34xx PSD module Table 135. Latc
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uPSD34xx PSD module mode, making th
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uPSD34xx PSD module See Figure 85 f
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uPSD34xx PSD module if they are use
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uPSD34xx PSD module Figure 88. Port
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uPSD34xx PSD module register to “
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uPSD34xx PSD module 28.5.52 Automat
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uPSD34xx PSD module Figure 89. Auto
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uPSD34xx PSD module of PLD input tr
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uPSD34xx PSD module In PLD I/O mode
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uPSD34xx PSD module Figure 91. JTAG
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uPSD34xx PSD module TSTAT and TERR
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uPSD34xx PSD module Figure 95. Exam
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uPSD34xx AC/DC parameters 29 AC/DC
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uPSD34xx AC/DC parameters I CC (MCU
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uPSD34xx DC and AC parameters 31 DC
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uPSD34xx DC and AC parameters Idle
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uPSD34xx DC and AC parameters Table
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uPSD34xx DC and AC parameters Figur
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uPSD34xx DC and AC parameters Note:
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uPSD34xx DC and AC parameters Symbo
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uPSD34xx DC and AC parameters Symbo
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uPSD34xx Package mechanical informa
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uPSD34xx Important notes 34 Importa
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uPSD34xx Important notes implemente
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uPSD34xx Important notes 34.12 Inco
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uPSD34xx Please Read Carefully: Inf
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