uPSD3434EB40U6

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Contents uPSD34xx 8/293 34.7 IN FIFO Pairing Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 34.8 OUT FIFO Pairing Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 34.9 Missing ACK to host retransmission of SETUP packet . . . . . . . . . . . . . 289 34.10 MCU JTAG ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 34.11 PORT 1 Not 5-volt IO Tolerant . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 34.12 Incorrect Code Execution when Code Banks are Switched . . . . . . . . . . 291 34.13 9th Received Data Bit Corrupted in UART Modes 2 and 3 . . . . . . . . . . 291 35 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
uPSD34xx Summary description 1 Summary description The Turbo Plus uPSD34xx Series combines a powerful 8051-based microcontroller with a flexible memory structure, programmable logic, and a rich peripheral mix to form an ideal embedded controller. At its core is a fast 4-cycle 8032 MCU with a 4-byte instruction prefetch queue (PFQ) and a 4-entry fully associative branching cache (BC). The MCU is connected to a 16-bit internal instruction path to maximize performance, enabling loops of code in smaller localities to execute extremely fast. The 16-bit wide instruction path in the Turbo Plus Series allows double-byte instructions to be fetched from memory in a single memory cycle. This keeps the average performance near its peak performance (peak performance for 5V, 40MHz Turbo Plus uPSD34xx is 10 MIPS for single-byte instructions, and average performance will be approximately 9 MIPS for mix of single- and multi-byte instructions). USB 2.0 (full speed, 12Mbps) is included, providing 10 endpoints, each with its own 64-byte FIFO to maintain high data throughput. Endpoint 0 (Control Endpoint) uses two of the 10 endpoints for In and Out directions, the remaining eight endpoints may be allocated in any mix to either type of transfers: Bulk or Interrupt. Code development is easily managed without a hardware In-Circuit Emulator by using the serial JTAG debug interface. JTAG is also used for In-System Programming (ISP) in as little as 10 seconds, perfect for manufacturing and lab development. The 8032 core is coupled to Programmable System Device (PSD) architecture to optimize the 8032 memory structure, offering two independent banks of Flash memory that can be placed at virtually any address within 8032 program or data address space, and easily paged beyond 64K bytes using onchip programmable decode logic. Dual Flash memory banks provide a robust solution for remote product updates in the field through In-Application Programming (IAP). Dual Flash banks also support EEPROM emulation, eliminating the need for external EEPROM chips. General purpose programmable logic (PLD) is included to build an endless variety of gluelogic, saving external logic devices. The PLD is configured using the software development tool, PSDsoft Express, available from the web at www.st.com/psm, at no charge. The uPSD34xx also includes supervisor functions such as a programmable watchdog timer and low-voltage reset. Note: For a list of known limitations of the uPSD34xx devices, please refer to Section 34: Important notes. 9/293
Page 1 and 2: Features summary uPSD34xx Turbo Plu
Page 3 and 4: uPSD34xx Contents Contents 1 Summar
Page 5 and 6: uPSD34xx Contents 18.3 Connecting e
Page 7: uPSD34xx Contents 27.5 Timer mode .
Page 11 and 12: uPSD34xx Pin descriptions 2 Pin des
Page 13 and 14: uPSD34xx Pin descriptions Table 2.
Page 15 and 16: uPSD34xx Pin descriptions Table 2.
Page 17 and 18: uPSD34xx Hardware description 3 Har
Page 19 and 20: uPSD34xx Memory organization 4 Memo
Page 21 and 22: uPSD34xx Memory organization 4.2.1
Page 23 and 24: uPSD34xx 8032 MCU core performance
Page 25 and 26: uPSD34xx 8032 MCU core performance
Page 27 and 28: uPSD34xx MCU module description 6 M
Page 29 and 30: uPSD34xx 8032 MCU registers the B R
Page 31 and 32: uPSD34xx Special function registers
Page 39 and 40: uPSD34xx 8032 addressing modes 9.4
Page 41 and 42: uPSD34xx 8032 addressing modes addr
Page 43 and 44: uPSD34xx uPSD34xx instruction set s
Page 45 and 46: uPSD34xx uPSD34xx instruction set s
Page 47 and 48: uPSD34xx Dual data pointers 11 Dual
Page 49 and 50: uPSD34xx Dual data pointers LOOP: M
Page 51 and 52: uPSD34xx Debug unit up to VCC as de
Page 53 and 54: uPSD34xx Interrupt system If an int
Page 55 and 56: uPSD34xx Interrupt system 13.1 Indi
Page 57 and 58: uPSD34xx Interrupt system Table 18.
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uPSD34xx MCU clock generation 14 MC
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uPSD34xx MCU clock generation Figur
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uPSD34xx Power saving modes 15 Powe
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uPSD34xx Power saving modes Table 2
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uPSD34xx Oscillator and external co
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uPSD34xx I/O ports of mcu module 17
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uPSD34xx I/O ports of mcu module CP
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uPSD34xx I/O ports of mcu module Ta
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uPSD34xx I/O ports of mcu module ou
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uPSD34xx I/O ports of mcu module Ta
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uPSD34xx MCU bus interface A[10:8]
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uPSD34xx MCU bus interface Table 37
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uPSD34xx Supervisory functions 19 S
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uPSD34xx Supervisory functions To p
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uPSD34xx Standard 8032 timer/counte
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uPSD34xx Serial UART interfaces 21
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uPSD34xx Serial UART interfaces SM2
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uPSD34xx Serial UART interfaces 21.
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uPSD34xx Serial UART interfaces Fig
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uPSD34xx IrDA interface 22 IrDA int
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uPSD34xx IrDA interface Table 51. B
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uPSD34xx I 2 C interface 23 I 2 C i
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uPSD34xx I 2 C interface A few thin
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uPSD34xx I 2 C interface 23.6 Gener
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uPSD34xx I 2 C interface 23.8 I 2 C
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uPSD34xx I 2 C interface Table 56.
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uPSD34xx I 2 C interface 23.12 I 2
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uPSD34xx I 2 C interface Table 62.
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uPSD34xx I 2 C interface Set global
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uPSD34xx I 2 C interface Else If mo
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uPSD34xx I 2 C interface Does statu
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uPSD34xx SPI (synchronous periphera
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uPSD34xx USB interface 25 USB inter
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uPSD34xx USB interface 25.1.2 Endpo
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uPSD34xx USB interface 25.2 Types o
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uPSD34xx USB interface Figure 53. C
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uPSD34xx USB interface Figure 54. F
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uPSD34xx USB interface Command Valu
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uPSD34xx USB interface Table 70. US
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uPSD34xx USB interface ● USB IN F
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uPSD34xx USB interface ● USB Glob
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uPSD34xx USB interface ● USB OUT
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uPSD34xx USB interface ● USB Cont
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uPSD34xx USB interface ● USB Endp
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uPSD34xx USB interface Bit Symbol R
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uPSD34xx USB interface ● USB Setu
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uPSD34xx Analog-to-digital converto
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uPSD34xx Analog-to-digital converto
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uPSD34xx Programmable counter array
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uPSD34xx PSD module 28 PSD module T
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uPSD34xx PSD module 28.1.5 SRAM pro
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uPSD34xx PSD module 28.1.11 OMCs sm
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uPSD34xx PSD module 28.1.16 Power m
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uPSD34xx PSD module Table 103. HDL
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uPSD34xx PSD module Figure 67. Mapp
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uPSD34xx PSD module 28.2.7 The VM r
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uPSD34xx PSD module Note: x = NA Th
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uPSD34xx PSD module Register Name P
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uPSD34xx PSD module Table 107. Flas
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uPSD34xx PSD module 28.5.7 Toggle f
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uPSD34xx PSD module attempted to pr
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uPSD34xx PSD module indicate when a
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uPSD34xx PSD module If a Suspend Se
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uPSD34xx PSD module The DPLD perfor
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uPSD34xx PSD module Figure 74. DPLD
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uPSD34xx PSD module Figure 75. DPLD
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uPSD34xx PSD module 28.5.28 Output
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uPSD34xx PSD module Native product
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uPSD34xx PSD module 28.5.32 OMC mas
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uPSD34xx PSD module 28.5.34 I/O por
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uPSD34xx PSD module Port Operating
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uPSD34xx PSD module Table 126. MCU
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uPSD34xx PSD module After PSDsoft E
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uPSD34xx PSD module Table 135. Latc
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uPSD34xx PSD module mode, making th
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uPSD34xx PSD module See Figure 85 f
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uPSD34xx PSD module if they are use
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uPSD34xx PSD module Figure 88. Port
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uPSD34xx PSD module register to “
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uPSD34xx PSD module 28.5.52 Automat
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uPSD34xx PSD module Figure 89. Auto
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uPSD34xx PSD module of PLD input tr
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uPSD34xx PSD module In PLD I/O mode
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uPSD34xx PSD module Figure 91. JTAG
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uPSD34xx PSD module TSTAT and TERR
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uPSD34xx PSD module Figure 95. Exam
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uPSD34xx AC/DC parameters 29 AC/DC
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uPSD34xx AC/DC parameters I CC (MCU
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uPSD34xx DC and AC parameters 31 DC
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uPSD34xx DC and AC parameters Idle
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uPSD34xx DC and AC parameters Table
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uPSD34xx DC and AC parameters Figur
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uPSD34xx DC and AC parameters Note:
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uPSD34xx DC and AC parameters Symbo
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uPSD34xx DC and AC parameters Symbo
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uPSD34xx Package mechanical informa
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uPSD34xx Important notes 34 Importa
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uPSD34xx Important notes implemente
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uPSD34xx Important notes 34.12 Inco
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uPSD34xx Please Read Carefully: Inf
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