vector - Department of Computer Science

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Vector Execution Time Time = f(vector length, data dependencies, struct. hazards) • Initiation rate: rate that FU consumes vector elements (= number of lanes; usually 1 or 2 on Cray T-90) • Convoy: set of vector instructions that can begin execution on same clock (if no structural or data hazards) • Chime: approximate time for a vector operation • m convoys take m chimes; if each vector length is n, then they take approx. m x n clock cycles if no chaining (ignores overhead; good approximization for long vectors) and as little as m + n - 1 cycles, if fully chained. 1: LV V1,Rx ;load vector X 2: MULV V2,F0,V1 ;vector-scalar mult. LV V3,Ry ;load vector Y 3: ADDV V4,V2,V3 ;add 4: SV Ry,V4 ;store the result 4 convoys, 1 lane, VL=64 => 4 x 64 = 256 clocks (or 4 clocks per result) 3/22-24/11 CSE502-S11, Lec 14+15-Vector 10
Memory operations • Load/store operations move groups of data between registers and memory • Three types of addressing – Unit stride » Contiguous block of information in memory » Fastest: always possible to optimize this – Non-unit (constant) stride » Harder to optimize memory system for all possible strides » Prime number of data banks makes it easier to support different strides at full bandwidth (Duncan Lawrie patent) – Indexed (gather-scatter) » Vector equivalent of register indirect » Good for sparse arrays of data » Increases number of programs that vectorize 3/22-24/11 CSE502-S11, Lec 14+15-Vector 11
Page 1 and 2: CSE 502 Graduate Computer Architect
Page 3 and 4: Scalar Registers r15 r0 Vector Prog
Page 5 and 6: Vector Arithmetic Execution • Use
Page 7 and 8: Properties of Vector Processors •
Page 9: Common Vector Metrics • R ∞ : M
Page 13 and 14: How Get Full Bandwidth if Unit Stri
Page 15 and 16: Single-issue Scalar Vectors Lower P
Page 17 and 18: Outline • Vector Processing Overv
Page 19 and 20: Supercomputers “Definitions” of
Page 21 and 22: Single Ported Memory 16 banks of 64
Page 23 and 24: Vector Memory-Memory versus Vector
Page 25 and 26: Vector Memory-Memory vs. Vector Reg
Page 27 and 28: Modern Vector Supercomputer: NEC SX
Page 29 and 30: NEC ESS - Earth Simulator System (n
Page 31 and 32: ESS - complete system installed 4/1
Page 33 and 34: Outline • Vector Processing Overv
Page 35 and 36: Vector Registers Lane Vector Unit S
Page 37 and 38: Vector Stripmining Problem: Vector
Page 39 and 40: Vector Chaining • Vector version
Page 41 and 42: Vector Startup Two components of ve
Page 43 and 44: Vector Scatter/Gather Want to vecto
Page 45 and 46: Scatter example: Vector Scatter/Gat
Page 47 and 48: Masked Vector Instruction Implement
Page 49 and 50: Vector Reductions (vector values =>
Page 51: And in Conclusion [Vector Processin

vector - Department of Computer Science

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