vector - Department of Computer Science

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Vector Instruction Set Advantages • Compact – one short instruction encodes N operations => N*FlOp BandWidth • Expressive, tells hardware that these N operations: – are independent – use the same functional unit – access disjoint registers – access registers in the same pattern as previous instructions – access a contiguous block of memory (unit-stride load/store) OR • Scalable access memory in a known pattern (strided load/store) – can run same object code on more parallel pipelines or lanes 3/22-24/11 CSE502-S11, Lec 14+15-Vector 6
Properties of Vector Processors • Each result independent of previous result => long pipeline, compiler ensures no dependencies => high clock rate • Vector instructions access memory with known pattern => highly interleaved memory => amortize memory latency of 64-plus elements => no (data) caches required! (but use instruction cache) • Reduces branches and branch problems in pipelines • Single vector instruction implies lots of work (≈ loop) => fewer instruction fetches 3/22-24/11 CSE502-S11, Lec 14+15-Vector 7
Page 1 and 2: CSE 502 Graduate Computer Architect
Page 3 and 4: Scalar Registers r15 r0 Vector Prog
Page 5: Vector Arithmetic Execution • Use
Page 9 and 10: Common Vector Metrics • R ∞ : M
Page 11 and 12: Memory operations • Load/store op
Page 13 and 14: How Get Full Bandwidth if Unit Stri
Page 15 and 16: Single-issue Scalar Vectors Lower P
Page 17 and 18: Outline • Vector Processing Overv
Page 19 and 20: Supercomputers “Definitions” of
Page 21 and 22: Single Ported Memory 16 banks of 64
Page 23 and 24: Vector Memory-Memory versus Vector
Page 25 and 26: Vector Memory-Memory vs. Vector Reg
Page 27 and 28: Modern Vector Supercomputer: NEC SX
Page 29 and 30: NEC ESS - Earth Simulator System (n
Page 31 and 32: ESS - complete system installed 4/1
Page 33 and 34: Outline • Vector Processing Overv
Page 35 and 36: Vector Registers Lane Vector Unit S
Page 37 and 38: Vector Stripmining Problem: Vector
Page 39 and 40: Vector Chaining • Vector version
Page 41 and 42: Vector Startup Two components of ve
Page 43 and 44: Vector Scatter/Gather Want to vecto
Page 45 and 46: Scatter example: Vector Scatter/Gat
Page 47 and 48: Masked Vector Instruction Implement
Page 49 and 50: Vector Reductions (vector values =>
Page 51: And in Conclusion [Vector Processin

vector - Department of Computer Science

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