vector - Department of Computer Science

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Vector Memory-Memory vs. Vector Register Machines • Vector memory-memory architectures (VMMA) require greater main memory bandwidth, why? – :All operands must be read in and out of memory • VMMAs make if difficult to overlap execution of multiple vector operations, why? – :Must check dependencies on memory addresses • VMMAs incur greater startup latency – Scalar code was faster on CDC Star-100 for vectors < 100 elements – For Cray-1, vector/scalar breakeven point was around 2 elements ⇒ Apart from CDC follow-ons (Cyber-205, ETA-10) all major vector machines since Cray-1 have had vector register architectures (we ignore vector memory-memory from now on) 3/22-24/11 CSE502-S11, Lec 14+15-Vector 24
Vector Memory-Memory vs. Vector Register Machines • Vector memory-memory architectures (VMMA) require greater main memory bandwidth, why? – :All operands must be read in and out of memory • VMMAs make if difficult to overlap execution of multiple vector operations, why? – :Must check dependencies on memory addresses • VMMAs incur greater startup latency – Scalar code was faster on CDC Star-100 for vectors < 100 elements – For Cray-1, vector/scalar breakeven point was around 2 elements ⇒ Apart from CDC follow-ons (Cyber-205, ETA-10) all major vector machines since Cray-1 have had vector register architectures (we ignore vector memory-memory from now on) 3/22-24/11 CSE502-S11, Lec 14+15-Vector 25
Page 1 and 2: CSE 502 Graduate Computer Architect
Page 3 and 4: Scalar Registers r15 r0 Vector Prog
Page 5 and 6: Vector Arithmetic Execution • Use
Page 7 and 8: Properties of Vector Processors •
Page 9 and 10: Common Vector Metrics • R ∞ : M
Page 11 and 12: Memory operations • Load/store op
Page 13 and 14: How Get Full Bandwidth if Unit Stri
Page 15 and 16: Single-issue Scalar Vectors Lower P
Page 17 and 18: Outline • Vector Processing Overv
Page 19 and 20: Supercomputers “Definitions” of
Page 21 and 22: Single Ported Memory 16 banks of 64
Page 23: Vector Memory-Memory versus Vector
Page 27 and 28: Modern Vector Supercomputer: NEC SX
Page 29 and 30: NEC ESS - Earth Simulator System (n
Page 31 and 32: ESS - complete system installed 4/1
Page 33 and 34: Outline • Vector Processing Overv
Page 35 and 36: Vector Registers Lane Vector Unit S
Page 37 and 38: Vector Stripmining Problem: Vector
Page 39 and 40: Vector Chaining • Vector version
Page 41 and 42: Vector Startup Two components of ve
Page 43 and 44: Vector Scatter/Gather Want to vecto
Page 45 and 46: Scatter example: Vector Scatter/Gat
Page 47 and 48: Masked Vector Instruction Implement
Page 49 and 50: Vector Reductions (vector values =>
Page 51: And in Conclusion [Vector Processin

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