EtherCAT Slave Implementation Guide

1 - Introduction
The ESC processes EtherCAT frames on the fly and provides data for a local host controller or
digital I/Os via the Process Data Interface (PDI). PDI availabilities depend on the ESC type (Table
16). The PDI is either:
i. Up to 32 Bit digital I/O
ii. Serial Peripheral Interface (SPI)
iii. 8/16-bit synchronous/asynchronous Microcontroller Interface (MCI)
iv. With FPGA: specific on-board-bus (Avalon on Altera devices resp. OPB on Xilinx
devices)
Process data and parameters are exchanged via a DPRAM in the ESC. To ensure data
consistency appropriate mechanisms are provided by the ESC hardware (defined by the
EtherCAT protocol, e.g. SyncManager, chapter 1.3.4).
In case of an FPGA implementation, the ESC is realized as IP core to enable EtherCAT
communication and application-specific functions. The EtherCAT device functionality is
configurable with regard to the EtherCAT features such as number of FMMUs and SyncManagers,
DC support, PDI (chapter 2.3).
FPGA implementations are at option in two ways. One way is integrating ESC and a soft core µC
on the FPGA. As PDI the FPGA on-board bus is then used. Another option is using the FPGA
solely for the ESC functionality and connecting an external µC via µC/SPI, s. Figure 3.
Figure 3: FPGA Implementations of an EtherCAT Slave
A plug-in for Altera or Xilinx development environments is available to configure the IP Core. The
IP Core is provided by Beckhoff Automation GmbH and different license models are offered for
available FPGA devices.
• EEPROM (ESC configuration data and application specific data)
The EEPROM (Electrically Erasable Programmable Read-Only Memory, also called Slave
Information Interface, SII) contains hardware configuration information for the ESC which is loaded
to the ESC’s registers during power-up. The ESC registers are then e.g. configured for the PDI so
that the DPRAM can be accessed from the local µC.
The EEPROM can be written by the configuration tool (via EtherCAT) based on the ESI file. The
µC can also access the EEPROM if access rights are assigned. However, the EEPROM is always
accessed via the ESC, which in turn interfaces to it via Inter-Integrated Circuit (I 2 C) data bus.
ETG.2200 EtherCAT Slave Implementation Guide V2.0.0 I-15