AN-6094 Design Guideline for Flyback Charger Using FAN302HL/UL

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AN-6094 The recommendation for RVS1 design is to set RVS1 such that the minimum on time curve of Figure 16 can be fully utilized for the universal line range. It is typical to select RVS1 such that IVS.ON is around 180 µA for the minimum line voltage. Figure 16. Minimum On-Time vs. VS Pin Current (UL) A bypass capacitor of 22~68 pF placed closely between the VS and GND pins is recommended to bypass the switching noise. Too large a capacitor distorts VS voltage and deteriorates the output current regulation. The RC time constant of the bypass capacitor and voltage divider resistor should be
AN-6094 Once the power dissipation in the snubber is obtained, the snubber resistor is calculated as: 2 ( VRO + VOS) RCL = (38) PCLMP where RCL is the clamping resistor. The maximum ripple of the clamping capacitor voltage is obtained as: VRO + VOS Δ VCL = (39) CCLRCL fs In general, 5~10% ripple of the selected capacitor voltage is reasonable. The clamping capacitor should be ceramic or a material that offers low ESR. Electrolytic or tantalum capacitors are unacceptable. NP ( VO + VF) N S VDL Figure 17. RCD Clamping Circuit and Waveforms The leakage inductance measured with an LCR meter tends to be larger than the actual effective leakage inductance. Moreover, the effective output capacitance of the MOSFET is difficult to measure. The best way to obtain these parameters correctly is to use the drain voltage waveform as illustrated in Figure 18. Since Lm can be measured with an LCR meter, COSS and LLK can be calculated from the measured resonant period. In the clamping design in this section, the lossy discharge of the inductor and stray capacitance is not considered. In the actual converter, the loss in the clamping network is less than the designed value due to this effect. 2π LLKCOSS 2π LC m OSS Figure 18. Drain Voltage Waveform (Design Example) Assuming that 700 V MOSFET is used, the voltage overshoot to limit the maximum drain voltage below 600 V is: max VOS < 600V −VDL − VRO = 156 The leakage inductance and the effective output capacitance of MOSFET are calculated from the resonance waveform as 18 µH and 55 pF, respectively. The peak current of clamping diode is obtained as: PK PK 2 COSS 2 ICL = ( IDS ) − VOS = 325mA L © 2012 Fairchild Semiconductor Corporation www.fairchildsemi.com Rev. 1.0.0 • 9/27/12 11 LK The power dissipation in the clamping circuit is obtained as: 1 PK 2 VRO + VOS PCLMP = fSLLK( ICL ) = 0.194W 2 VOS Then the clamping circuit resistor is calculated as: 2 ( VRO + VOS ) RCL = = 263kΩ PCLMP The actual drain voltage can be lower than the design due to the loss of stray resistance of inductor and capacitor. The resistor value can be adjusted after the power supply is actually built. To allow less than 15 V ripple on the clamping capacitor voltage, the clamping capacitor should be: VRO + VOS CCL > = 410 pF C ΔV f CL CL s A 470 pF capacitor is selected. [STEP-7] Calculate the Voltage and Current of the Switching Devices Primary-Side MOSFET: The voltage stress of the MOSFET was discussed when determining the transformer turns ratio in STEP-6. The maximum voltage stress of the MOSFET is given in Equations (35). The rms current through the MOSFET is given as: t f 3 rms PK ON @ A s DS = (40) DS I I
Page 1 and 2: AN-6094 www.fairchildsemi.com Desig
Page 3 and 4: AN-6094 3. Design Consideration A b
Page 5 and 6: AN-6094 The input power of transfor
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Page 19 and 20: AN-6094 7. Test Results of Design E

AN-6094 Design Guideline for Flyback Charger Using FAN302HL/UL

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