AN-9732 - Fairchild Semiconductor

More documents

Recommendations

Info

AN-9732 APPLICATION NOTE 2. 5 115mho fI V 2 C f CP OUT 2 R COMP GM 115 mho COMP, LF 1 C COMP, HF [ Hz] [ Hz] Figure 27. Compensation Network (31) The feedback resistor is chosen to scale down the output voltage to meet the internal reference voltage: R R FB1 FB1 R FB2 V OUT 2. 5V (32) Typically, high RFB1 is used to reduce power consumption and, at the same time, CFB can be added to raise the noise immunity. The maximum CFB currently used is several nano farads. Adding a capacitor at the feedback loop introduces a pole as: f FP 2 1 2 R 1 R// R FB1 FB2 C FB where R// R FB1 FB2 C [ Hz] FB RFB1 RFB2 FB2 RFB1 RFB2 (33) Though RFB1 is high, pole frequency made by the synthesized total resistance and several nano farads is several kilo hertz and rarely affects control-loop response. The procedure to design the feedback loop is: a. Determine the crossover frequency (fC) around 1/10~1/5 of line frequency. Since the control-tooutput transfer function of the power stage has -20dB/dec slope and -90 o phase at the crossover frequency, as shown in Figure 28; it is required to place the zero of the compensation network (fCZ) around the crossover frequency so 45 phase margin is obtained. The capacitor CCOMP,LF is determined as: V 2 KSAW LINE 2. 5 115mho CCOMP, LF [ f ] 2 2 (34) 2VOUT L COUT2fC To place the compensation zero at the crossover frequency, the compensation resistor is obtained as: 1 2 f C © 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com Rev. 1.0.0 • 3/23/11 14 R COMP C COMP, LF [ ] (35) b. Place this compensator high-frequency pole (fCP) at least a decade higher than fC to ensure that it does not interfere with the phase margin of the voltage regulation loop at its crossover frequency. It should also be sufficiently lower than the switching frequency of the converter for noise to be effectively attenuated. The capacitor CCOMP,HF is determined as: C COMP, HF 1 [ ] (36) 2 f R CP COMP Figure 28. Compensation Network Design
AN-9732 APPLICATION NOTE (Design Example) IfRFB1 is 11.7M, then RFB2 is: 2. 5V 2. 5 6 RFB2 RFB1 11. 710 73. 58k VOUT 2. 5V 400 2. 5 Choosing the crossover frequency (control bandwidth) at 15Hz, CCOMP,LF is obtained as: V 2 K SAW LINE 2. 5115 mho CCOMP , LF 2 2 2 VOUT L COUT 2fC 6 2 6 8. 496 10 230 2. 511510 950. 13nF 2 6 6 2 2 400 199 10 240 10 215 Actual CCOMP,LF is determined as 1000nF since it is the closest value among the off-the-shelf capacitors. RCOMP is obtained as: 1 1 RCOMP 11. 17k 2 f C 9 C COMP, LF 2 15950. 110 Selecting the high-frequency pole as 150Hz, CCOMP,HF is obtained as: 1 1 CCOMP, HF 95. 01nF 2 fCP R 3 COMP 2 15011. 1710 These components result in a control loop with a bandwidth of 19.5Hz and phase margin of 45.6. The actual bandwidth is a little larger than the asymptotic design. [STEP-10] Line Filter Capacitor Selection It is typical to use small bypass capacitors across the bridge rectifier output stage to filter the switching current ripple, as shown in Figure 29. Since the impedance of the line filter inductor at line frequency is negligible compared to the impedance of the capacitors, the line frequency behavior of the line filter stage can be modeled, as shown in Figure 29. Even though the bypass capacitors absorb switching ripple current, they also generate circulating capacitor current, which leads the line voltage by 90 o , as shown in Figure 30. The circulating current through the capacitor is added to the load current and generates displacement between line voltage and current. The displacement angle is given by: V 2 1 LINE 2 fLINEC EQ tan (37) P OUT where CEQ is the equivalent capacitance that appears across the AC line (CEQ=CF1+CF2+CHF). The resultant displacement factor is: © 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com Rev. 1.0.0 • 3/23/11 15 DF cos (38) Since the displacement factor is related to power factor, the capacitors in the line filter stage should be selected carefully. With a given minimum displacement factor (DFMIN) at full-load condition, the allowable effective input capacitance is obtained as: V 1 cos DF [ F ] POUT CEA tan 2 MN 2 f LINE LINE (39) One way to determine if the input capacitor is too high or PFC control routine has problems is to check Power Factor (PF) and Total Harmonic Distortion (THD). PF is the degree to which input energy is effectively transferred to the load by the multiplication of displacement factor and THD that is input current shape deterioration ratio. PFC control loop rarely has no relation to displacement factor and input capacitor rarely has no impact on the input current shape. If PF is low (high is preferable), but THD is quite good (low is preferable), it can be concluded that input capacitance is too high and PFC controller is fine. (Design Example) Assuming the minimum displacement factor at full load is 0.98, the equivalent input capacitance is obtained as: POUT 1 CEA tancos DF 2 MN VLINE 2 fLINE 200 1 tancos 0. 982. 0453F 2 0. 9 264 2 50 Thus, the sum of the capacitors on the input side should be smaller than 2.0µF.
Page 1 and 2: AN-9732 www.fairchildsemi.com LED A
Page 3 and 4: AN-9732 APPLICATION NOTE Figure 4.
Page 5 and 6: AN-9732 APPLICATION NOTE [STEP-1] D
Page 7 and 8: AN-9732 APPLICATION NOTE [STEP-3] I
Page 9 and 10: AN-9732 APPLICATION NOTE Figure 19.
Page 11 and 12: AN-9732 APPLICATION NOTE (Design Ex
Page 13: AN-9732 APPLICATION NOTE [STEP-9] D
Page 17 and 18: AN-9732 APPLICATION NOTE Appendix 1
Page 19 and 20: AN-9732 APPLICATION NOTE Appendix 3
Page 21 and 22: AN-9732 APPLICATION NOTE RFB2 is th

AN-9732 - Fairchild Semiconductor

You also want an ePaper? Increase the reach of your titles

Delete template?

Save as template?