Appendix G - Clemson University

We want Time 1 ≥ Time 2 , so
G.4 Enhancing Vector Performance ■ G-29
That is, the second method is faster if less than one-quarter of the elements are
nonzero. In many cases the frequency of execution is much lower. If the index
vector can be reused, or if the number of vector statements within the if statement
grows, the advantage of the scatter-gather approach will increase sharply.
Multiple Lanes
Time1 = 5( n)
Time2 = 4n + 4 fn
5n ≥ 4n + 4 fn
1
-- ≥
f
4
One of the greatest advantages of a vector instruction set is that it allows software
to pass a large amount of parallel work to hardware using only a single short
instruction. A single vector instruction can include tens to hundreds of independent
operations yet be encoded in the same number of bits as a conventional scalar
instruction. The parallel semantics of a vector instruction allows an
implementation to execute these elemental operations using either a deeply pipelined
functional unit, as in the VMIPS implementation we’ve studied so far, or by
using an array of parallel functional units, or a combination of parallel and pipelined
functional units. Figure G.11 illustrates how vector performance can be
improved by using parallel pipelines to execute a vector add instruction.
The VMIPS instruction set has been designed with the property that all vector
arithmetic instructions only allow element N of one vector register to take part in
operations with element N from other vector registers. This dramatically simplifies
the construction of a highly parallel vector unit, which can be structured as
multiple parallel lanes. As with a traffic highway, we can increase the peak
throughput of a vector unit by adding more lanes. The structure of a four-lane
vector unit is shown in Figure G.12.
Each lane contains one portion of the vector-register file and one execution
pipeline from each vector functional unit. Each vector functional unit executes
vector instructions at the rate of one element group per cycle using multiple pipelines,
one per lane. The first lane holds the first element (element 0) for all vector
registers, and so the first element in any vector instruction will have its source and
destination operands located in the first lane. This allows the arithmetic pipeline
local to the lane to complete the operation without communicating with other
lanes. Interlane wiring is only required to access main memory. This lack of interlane
communication reduces the wiring cost and register file ports required to
build a highly parallel execution unit, and helps explains why current vector
supercomputers can complete up to 64 operations per cycle (2 arithmetic units
and 2 load-store units across 16 lanes).