Appendix G - Clemson University

G-42 ■ Appendix G Vector Processors
the Cray-1 became sufficient for a loop that formerly required more bandwidth.
This ability to reuse values from vector registers is another advantage of vectorregister
architectures compared with memory-memory vector architectures,
which have to fetch all vector operands from memory, requiring even greater
memory bandwidth.
G.8 Concluding Remarks
During the 1980s and 1990s, rapid performance increases in pipelined scalar
processors led to a dramatic closing of the gap between traditional vector supercomputers
and fast, pipelined, superscalar VLSI microprocessors. In 2002, it is
possible to buy a complete desktop computer system for under $1000 that has a
higher CPU clock rate than any available vector supercomputer, even those costing
tens of millions of dollars. Although the vector supercomputers have lower clock
rates, they support greater parallelism through the use of multiple lanes (up to 16
in the Japanese designs) versus the limited multiple issue of the superscalar microprocessors.
Nevertheless, the peak floating-point performance of the low-cost
microprocessors is within a factor of 4 of the leading vector supercomputer CPUs.
Of course, high clock rates and high peak performance do not necessarily translate
into sustained application performance. Main memory bandwidth is the key distinguishing
feature between vector supercomputers and superscalar microprocessor
systems. The fastest microprocessors in 2002 can sustain around 1 GB/sec of main
memory bandwidth, while the fastest vector supercomputers can sustain around 50
GB/sec per CPU. For nonunit stride accesses the bandwidth discrepancy is even
greater. For certain scientific and engineering applications, performance correlates
directly with nonunit stride main memory bandwidth, and these are the applications
for which vector supercomputers remain popular.
Providing this large nonunit stride memory bandwidth is one of the major
expenses in a vector supercomputer, and traditionally SRAM was used as main
memory to reduce the number of memory banks needed and to reduce vector
start-up penalties. While SRAM has an access time several times lower than that
of DRAM, it costs roughly 10 times as much per bit! To reduce main memory
costs and to allow larger capacities, all modern vector supercomputers now use
DRAM for main memory, taking advantage of new higher-bandwidth DRAM
interfaces such as synchronous DRAM.
This adoption of DRAM for main memory (pioneered by Seymour Cray in
the Cray-2) is one example of how vector supercomputers are adapting commodity
technology to improve their price-performance. Another example is that vector
supercomputers are now including vector data caches. Caches are not
effective for all vector codes, however, and so these vector caches are designed to
allow high main memory bandwidth even in the presence of many cache misses.
For example, the cache on the Cray SV1 can support 384 outstanding cache
misses per CPU, while for microprocessors 8–16 outstanding misses is a more
typical maximum number.