Optimization of a SiGe:C HBT in a BiCMOS Technology ... - Freescale

Optimization of a SiGe:C HBT in a BiCMOS Technology for Low Power Wireless
Applications
Jay P. John, Francis Chai, Dave Morgan, Theresa Keller, Jim Kirchgessner, Ralf Reuter † , Hernan Rueda, Jim Teplik, Jan White,
Sandy Wipf, Dragan Zupac
Digital DNA TM Laboratories, Semiconductor Products Sector, Motorola Inc, Tempe AZ, † Berlin, Germany
2100 E. Elliot Rd, MD: EL741, Tempe, AZ, 85284. Phone: (480) 413-3784, FAX: (480) 413-7950, Email: jay.john@motorola.com
ABSTRACT
The performance enhancement of a SiGe:C HBT for RF/IF
applications is described for Motorola’s 0.35µm and 0.18µm
BiCMOS technologies. Cutoff frequencies (fT) have been
improved from 50GHz to 78/84GHz (0.35/0.18µm BiCMOS),
with a reduction in minimum noise figure (NF) from 0.7dB to
0.3dB. Improvements occurred through the optimization of the
intrinsic collector and base dopant profiles, extrinsic collector
resistance, and device layout.
INTRODUCTION
Silicon germanium (SiGe) technology is rapidly becoming
the technology of choice for many wireless applications as
consumer demand for low power portable products continues to
increase [1] - [5]. SiGe offers the opportunity for integrating a
high performance HBT with CMOS analog and digital functions
on a single chip. Foremost on the list of desirable attributes for
these transistors is higher performance at lower currents as well
as high gain and low noise figure at frequencies up to 10GHz.
The ability to integrate an HBT device in a standard CMOS
technology platform is highly desirable in order to leverage the
use of existing CMOS models, libraries, and standard cell
designs. This objective, as well as the desire to maximize HBT
performance, presents a difficult challenge. On the one hand, it
is essential that the thermal cycles associated with the HBT
module (and exactly how they are integrated with the CMOS
platform) do not perturb the platform device parametrics; on the
other hand, it is equally important that the thermal cycles
associated with the CMOS platform do not excessively limit the
performance of the HBT.
Carbon doping in the base of a SiGe HBT can help alleviate
these opposing constraints. Carbon significantly reduces base
profile spreading and controls TED effects associated with the
extrinsic base and self-aligned collector implantations [6], [7].
This means that with carbon doping the HBT is less affected by
thermal cycling from the CMOS platform technology. The
reduced boron diffusion also enables a much higher base doping
to be used with intrinsic base resistance values as low as
1.6kΩ/sq [9]. This key feature allows the use of a very simple,
highly manufacturable “quasi-self-aligned” (QSA) device
structure while still maintaining outstanding fMAX and noise
performance.
In this paper, we describe the performance enhancement of
the SiGe:C HBT used in Motorola’s 0.35µm and 0.18µm RF-
BiCMOS technologies. The goal of these enhancements is to
improve peak fT by 50%, while reducing the current required for
fT=50GHz by at least 2x. Careful optimization of the layout,
collector doping profiles (both intrinsic and extrinsic), as well as
the base and emitter doping profiles is required. This paper
discusses the opportunities and trade-offs associated with
various approaches to modifying the device design to optimize
key performance characteristics.
BASELINE TECHNOLOGIES
To satisfy the present and emerging needs for wireless RF
applications, Motorola has developed two highly cost-effective
SiGe:C RF-BiCMOS technologies, based on existing 0.35µm
and 0.18µm CMOS process platforms [8], [9]. Although these
technologies have been described elsewhere, the salient features
will be reviewed briefly here. Figure 1 illustrates the basic HBT
structure for each of these technologies. The HBT emitter/base
structure is essentially identical for these technologies, with the
most significant differences being in design rules. The collector
structures are different, however, with the 0.35µm process
including a buried layer (optimized for an isolated NMOS
device) as well as LOCOS and deep trench isolation. The
0.18µm process utilizes only shallow trench isolation and a
high-energy implanted collector well to minimize overall
complexity. Table 1 gives a brief comparison of some of the
key device parameters. A key objective in the design of each of
these technologies has been outstanding manufacturability,
demonstrated by typical yields of >95% for arrays of 5000+
HBTs. It is important to note that for the HBT performance
enhancements reported in this paper, the CMOS and passive
device parameters are unchanged from those reported in the
baseline BiCMOS technologies [8], [9].
In this paper we will describe some of the work done to
evaluate extending the performance of the 0.35µm and 0.18µm
BiCMOS HBT devices to achieve peak cutoff frequencies in the
range of 75GHz and to increase cutoff frequencies at lower
currents in order to satisfy the requirements for lower power and
higher frequency wireless applications. We include both
measured data as well as simulated data using a complete 2-D
structure which accounts for both intrinsic and extrinsic effects.
Some of the obvious opportunities for performance
improvement include: 1) intrinsic collector doping scaling, 2)
intrinsic emitter/base profile scaling, 3) extrinsic collector
construction improvement, 4) device layout optimization .
INTRINSIC PROFILE IMPROVEMENTS
For better visualization, the basic HBT transit time equation
(in simple form) is given below in Eq. (1) – Eq. (4):

τEC = τE + τB + τC (1)
where,
τE = (VT/IC)*(CJE + CN) (2)
τB = WB 2 /2*Dn (3)
τC = WC/(2*vsat) + CJC*(RC+ RE) + CJC* VT/IC (4)
One of the most straightforward ways to increase fT is to
increase the intrinsic collector doping at the C-B junction to
allow a higher collector current which decreases the effects of
the capacitance terms (~1/IC). An example of this is shown in
Figure 2. These plots give both measured and simulated results
from the 0.35µm process. Here, the collector doping was
increased from approximately 1x10 17 atoms/cm 3 to 4x10 17
atoms/cm 3 . This gives a small 10-15% boost in peak fT as the
Kirk effect is pushed out to higher currents. However, this
approach alone results in negligible performance improvement
at low currents, degradation in BVCEO, and degradation in the
fMAX/fT ratio (due to the increase in collector-base capacitance).
Clearly, this process modification by itself, offers only limited
advantages.
In order to address the τE and τB terms, the intrinsic base
profile must be modified. Figure 3 shows the influence of
reducing the base width with an adjustment to the base position
relative to the germanium edge at the emitter-base junction. The
increase in Beta through this approach reduces τE (reduced VBE
for a given IC) as well as reduces τB due to base width
reduction. This approach is more desirable than a strict
collector doping increase. Here, a 20% increase in peak fT is
realized, with a significant improvement in low current
behavior. For example, the current required to operate at
40GHz is reduced by a factor of 2x in this case.
Another approach to modifying the emitter-base junction
characteristics is to modify the Si cap thickness, or depth of the
boron and Ge profile in the SiGe:C epitaxial film. This region
of the intrinsic profile provides a buffer between the base
doping and the in-situ doped emitter As diffusion. Reducing the
thickness of this layer is an approach frequently used to reduce
both the τB (by reducing the base width) and τE (by reducing
charge storage) terms. The impact of this approach has been
evaluated experimentally and through device simulations.
Simulated and measured peak fT data versus cap thickness is
given in Figure 4 for several base and collector profiles for the
0.18µm BiCMOS HBT. This approach to optimizing the
intrinsic profile represents one option for increasing peak fT.
However, this approach also has several potential drawbacks,
including degradation in E-B diode characteristics and the
associated HCI reliability, as well as increasing the emitter-base
capacitance CJE. The increase in CJE is especially important for
low current fT performance; at some point the increase in CJE
will offset the reduction in τB and τE and begin to degrade low
current fT. Therefore, the extent to which thinning the cap
region is a viable approach to improving device performance is
dependent upon the particular reliability and performance
targets. In the case of our baseline 0.35µm and 0.18µm
technologies, CJE is very low (as evidenced by BVEBO > 4V) and
therefore we expect some benefit from cap thickness reduction.
EXTRINSIC COLLECTOR IMPROVEMENTS
The effect of collector resistance was investigated both
experimentally and through the use of simulations. Figure 5
plots simulated peak fT versus collector resistance, and includes
a number of different collector and base doping profiles, such as
baseline base/collector doping, thin base, and higher collector
doping. Collector resistance was varied through a modification
of the buried layer doping and position as well as a modification
of the vertical collector contact resistance. For performance in
the 50GHz range collector resistance is important but not
limiting. However, as the base and collector profiles are
optimized for higher fT, collector resistance becomes
increasingly critical. Therefore, the tradeoffs with respect to
reducing the collector resistance while minimizing process
complexity become more significant and challenging. For
example, although a very shallow N+ buried layer (i.e. thin epi)
would favor optimal HBT performance, this solution may
impact other devices utilizing the same process feature (such as
an isolated NMOS device). If such interactions do exist,
additional process complexity may be required to reduce the
extrinsic collector resistance.
It was previously stated that although an increase in
collector doping can result in some increase in peak fT, by itself
it offers negligible benefit at lower current densities and can
degrade fMAX and BVCEO. If, however, the intrinsic profile has
been modified to reduce τE and τB and the extrinsic collector
resistance has also been reduced, fT may become limited by the
C-B space charge region width (WC/(2*vsat)). This can be
observed as a drop in peak fT with increasing VCE. Therefore,
an increase in intrinsic collector doping may be advantageous
once the other delay components are optimized. Figure 6 plots
fT versus collector current for the enhanced 0.35µm device
compared to the baseline 0.35µm device. A peak fT near 78GHz
is achieved through reduction in collector resistance, proper
modifications to the base profile, and an increase in the intrinsic
collector doping. The current required for 50GHz performance
is reduced by 4x. Figure 7 plots fT versus collector current for
the enhanced 0.18µm device compared to the baseline 0.18µm
device. A peak fT near 84GHz is achieved through a reduction
in Si cap thickness and similar modifications to the base and
collector profiles. For 50GHz performance, the current
consumption is reduced by 3x.
DEVICE LAYOUT IMPROVEMENTS
The base resistance of a QSA structure is essentially
determined by the emitter poly dimension, which includes both
the emitter width and the emitter poly "overlap" regions which
define the space between the intrinsic region and the extrinsic
base region. Noise figure and fMAX are critical figures of merit
for wireless applications and strongly correlate to this layout
dimension. Figure 8 shows fMAX and NFMIN @ 2GHz as a
function of emitter poly dimension for both the baseline 0.35µm
and 0.18µm technologies, in addition to fMAX for the enhanced
0.35µm and 0.18µm technologies. The graph highlights the key
lithography-driven parasitics for the QSA device architecture.
The 0.18µm process benefits from more advanced lithography
(both minimum dimension and emitter poly overlap of emitter
window). This also shows how the 0.35µm performance may

e improved with tighter process control. Figure 8 also shows
improved fMAX values for the 0.18µm and 0.35µm enhanced
HBT devices: 125/105GHz (0.18/0.35µm). Figure 9 shows the
influence of both layout and the base profile modifications
previously discussed on noise figure at 2GHz and 10GHz for the
0.35µm BiCMOS technology. NFMIN is reduced by >0.6dB at
both 2GHz and 10GHz through layout and base profile
modifications, with the device achieving an NFMIN of
0.3dB/1.1dB at 2GHz/10GHz. As evidenced from the data, this
reduction in NFMIN occurs over a wide range of frequency and
bias conditions.
SUMMARY AND CONCLUSIONS
Various process enhancements to 0.35µm and 0.18µm
SiGe:C BiCMOS technologies have been described. A peak fT
of 78GHz has been achieved for 0.35µm BiCMOS HBT while
increasing fMAX to 105GHz and decreasing NFMIN to 0.3dB @
2GHz. The 0.18µm BiCMOS HBT performance increased to
84GHz/125GHz fT/fMAX. A balanced combination of
modifications to the extrinsic collector resistance (τC), base
profile (τB and τE), collector doping (τC), and layout for the
0.35µm process (RB) resulted in a significant improvement in
overall device performance. Each of these modifications, by
itself, does not give a significant improvement in performance,
but taken together, they result in a 50% increase in peak fT and a
0.6dB reduction in noise figure.
ACKNOWLEDGMENTS
The authors wish to acknowledge the MOS11,
AMIDL/MOS12, and PMCL organizations for outstanding
wafer processing and analytical support. Special thanks to J.
Keys, H. Kretzschmar, Ron Cross, Chris Lesher, J. Hildreth, and
A. Morton for their process integration and SiGe:C epi
expertise.
REFERENCES
[1] S.A. St. Onge, et al, BCTM Proceedings, pp. 117, 1999.
[2] A. Monroy, et al., BCTM Proceedings, pp. 121, 1999.
[3] M. Racanelli, et al., BCTM Proceedings, pp. 125, 1999.
[4] K. Washio, et al., IEDM Technical Digest, 1999.
[5] C.A. King, et al., IEDM Technical Digest, 1999.
[6] H.J. Osten et al., BCTM Proceedings, pp. 109-116, 1999.
[7] K.E. Ehwald, et al., IEDM Technical. Digest, 1999.
[8] F.K. Chai, et al, BCTM Proceedings, pp.110-113, 2000.
[9] J. Kirchgessner, et al, BCTM Proceedings, pp. 151-154, 2001.
Technology
HBT Parameter 0.35µm 0.18µm
Beta 120 120
Early Voltage (V) 95 90
BVCEO (V) 3.4 3.3
fT @ 2V (GHz) 49 50
fMAX @ 2V (GHz) 86 110
IC @ Peak fT/fMAX (mA/µm 2 ) ~1.5 ~1.5
NFMIN @ 2GHz (dB) 0.9 0.75
Minimum WE (µm) 0.4 0.25
Intrinsic Base RS (Ohm/sq) 1.9k 1.6k
Table 1: Baseline HBT Parameter Comparison.
f T (GHz) @ V CE =2V
f T (GHz) @ V CE =2V
Figure 1: Schematic Illustration of the HBT Devices.
70
60
50
40
30
20
10
0
10 -5
0.35µm BiCMOS
10 -4
10 -3
1e17 at/cm 3 (measured)
4e17 at/cm 3 (measured)
1e17 at/cm 3 (simulated)
4e17 at/cm 3 (simulated)
10 -2
10 -1
Ic (A)
Figure 2: Effect of Intrinsic Collector Doping
on a 0.4x10 HBT.
70
60
50
40
30
20
10
B E C
0
10 -5
Collector Well
N+ Buried Layer
C
P- Substrate
B
Collector Well
P- Substrate
Narrow Base
STD Base
10 -4
10 -3
Ic (A)
NWell
0.35µm BiCMOS
E B C
0.18µm BiCMOS
0.35µm BiCMOS
10 -2
Figure 3: Effect of Base Profile Modifications
on a 0.4x10 HBT.
10 -1

Peak f T (GHz)
peak f T (GHz)
115.0
105.0
95.0
85.0
75.0
65.0
55.0
45.0
STD
STD Base, Mid-Collector Doping
STD Base, Hi-Collector Doping
Narrow Base, Mid-Collector Doping
Narrow Base, Hi-Collector Doping
15 25 35 45 55
Cap Thickness (Arbitrary Units)
Figure 4: Peak fT versus Si Cap Thickness for Various
Base/Collector Profiles; Measured Data (Filled
Symbols) and Simulated Data (Open Symbols)
80
75
70
65
60
55
50
45
f T (GHz) @ V CE =2V
80
70
60
50
40
30
20
10
0
0.18µm BiCMOS
Peak Cutoff Frequency vs. Collector Resistance
40
0 100 200 300 400 500 600 700 800
10 -5
Collector Resistance (Ohm*um)
STD
Enhanced
10 -4
Figure 6: Performance Enhancement: 0.35µm
BiCMOS, Modified Base/Collector Profile, Reduced
Collector Resistance (0.4x10 HBT).
10 -3
Ic (A)
Simulated (Enhanced)
Measured (Enhanced)
Simulated (Standard)
Measured (Standard)
Figure 5: Collector Resistance Effect on peak fT for Various
Base/Collector profiles.
0.35µm BiCMOS
4x IC
Reduction
10 -2
10 -1
f MAX @ V CE =2V (GHz)
f T (GHz) @ V CE =2V
NF MIN (dB)
100
90
80
70
60
50
40
30
20
10
0
10 -6
STD
Enhanced
0.18µm BiCMOS
10 -5
10 -4
Ic (A)
Figure 7: Performance Enhancement: 0.18µm
BiCMOS, Modified Base/Collector Profile, Reduced
Cap Thickness (0.25x10 HBT).
130
120
110
100
90
3.5
3.0
2.5
2.0
1.5
1.0
0.5
f MAX (STD)
f MAX (Enhanced)
2GHz (STD)
2GHz (Enhanced)
10GHz (STD)
10GHz (Enhanced)
10 -3
3x IC
Reduction
Figure 9: NFMIN versus Current Density at 2GHz
and 10GHz. Reduction of >0.6dB for Enhanced HBT.
10 -2
0.35um
0.8
0.18um Enhanced 0.35um
80
0.7
0.7 0.8 0.9 1 1.1 1.2
Emitter Poly CD (Arbitrary Units)
Figure 8: Layout Effect of Emitter Poly on fMAX,
NFMIN . NF data at 0.4mA/um 2 , 2GHz.
0.0
0 0.5 1 1.5 2
Current Density (mA/um 2 )
NF MIN
1.5
1.4
1.3
1.2
1.1
0.9
0.35µm BiCMOS
1
10 -1
NF MIN @ 2GHz, 0.4mA/um 2 (dB)